Semiconductor structure and method for preparing the same

Abstract

A semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.

1 . A semiconductor structure, comprising:
 a substrate having a first region and a second region;   a plurality of first line patterns positioned in the first region and extending along a first direction;   a plurality of second line patterns positioned over the first line patterns in the first region, wherein the plurality of second line patterns extend along a second direction substantially not perpendicular to the first direction; and   a plurality of linear features positioned in the second region;   wherein the plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a plurality of third line patterns disposed over the first line patterns in the first region, wherein the plurality of second line patterns and the plurality of third line patterns are disposed over the first line pattern in an alternate manner. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the plurality of second line patterns, the plurality of third line patterns, and the plurality of linear features are positioned at substantially the same level in the substrate. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the second region is in the absence of the first line patterns. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the plurality of linear features in the second region are integrally formed with the plurality of second line patterns in the first region. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the plurality of linear features in the second region are integrally formed with the plurality of third line patterns in the first region. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the first region is a memory array region, and the second region is a peripheral circuit region. 
     
     
         8 . A semiconductor structure, comprising:
 a substrate having a first region and a second region;   a plurality of island patterns positioned only in the first region; and   a plurality of linear features only in the second region;   wherein the plurality of island patterns and the plurality of linear features are positioned at substantially different levels in the substrate.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein the plurality of island patterns are positioned in the first region in an array manner, the array extends along a first direction and a second direction substantially not perpendicular to the first direction. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the plurality of linear features extend along the first direction in the second region. 
     
     
         11 . The semiconductor structure of  claim 8 , wherein the plurality of island patterns are positioned at a first level, the plurality of linear features are positioned at a second level, and the first level is substantially lower than the second level in the substrate. 
     
     
         12 . The semiconductor structure of  claim 8 , wherein the first region is a memory array region, and the second region is a peripheral circuit region. 
     
     
         13 . A method for preparing a semiconductor structure, comprising:
 forming a plurality of linear core patterns and a plurality of linear spacer patterns on a substrate, wherein the plurality of linear spacer patterns are formed on sidewalls of the linear core patterns;   removing the plurality of linear core patterns from the substrate;   removing a portion of the substrate not covered by the plurality of linear spacer patterns to form a plurality of first line patterns, wherein the plurality of first line patterns extend along a first direction;   performing a first litho-etch process to form a plurality of second line patterns over the first line patterns, wherein the plurality of second line patterns extend along a second direction different from the first direction; and   performing a second litho-etch process to form a plurality of third line patterns over the first line patterns, wherein the plurality of second line patterns and the plurality of third line patterns are formed over the first line pattern in an alternate manner   
     
     
         14 . The method for preparing a semiconductor structure of  claim 13 , wherein the second direction is substantially not perpendicular to the first direction. 
     
     
         15 . The method for preparing a semiconductor structure of  claim 13 , wherein the plurality of first line patterns are formed in a mask layer of the substrate, and a patterning process is performed using the plurality of second line patterns and the plurality of third line patterns to pattern the plurality of first line patterns into a plurality of island patterns. 
     
     
         16 . The method for preparing a semiconductor structure of  claim 13 , wherein the substrate comprises a first region and a second region, and the first litho-etch process and the second litho-etch process are performed to form the plurality of second line patterns and the plurality of third line patterns in the first region and a plurality of linear features in the second region. 
     
     
         17 . The method for preparing a semiconductor structure of  claim 16 , wherein the plurality of linear features in the second region are integrally formed with the plurality of second line patterns in the first region. 
     
     
         18 . The method for preparing a semiconductor structure of  claim 16 , wherein the plurality of linear features in the second region are integrally formed with the plurality of third line patterns in the first region. 
     
     
         19 . The method for preparing a semiconductor structure of  claim 13 , wherein the substrate comprises a first region and a second region, the plurality of first line patterns are formed in the first region, and the second region is in the absence of the first line patterns. 
     
     
         20 . The method for preparing a semiconductor structure of  claim 13 , wherein the forming of the plurality of first line patterns comprises performing an etching process using the plurality of linear spacer patterns as an etching mask.