Dynamic random access memory and method of manufacturing the same

Abstract

A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divide the substrate into active areas. The active areas are configured in the shape of band and arranged in an array. The word line sets are disposed in parallel in a Y direction in the substrate. The bit-line structures are disposed in parallel in an X direction on the substrate and cross the word line sets. The spacers are disposed in parallel in the X direction on sidewalls of the substrate, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminals of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active areas.

What is claimed is: 
     
         1 . A dynamic random access memory (DRAM), comprising:
 a plurality of isolation structures, located in a substrate to divide the substrate into a plurality of active areas, wherein the active areas are configured in a shape of band and arranged in an array;   a plurality of word line sets, disposed in parallel in a Y direction in the substrate;   a plurality of bit-line structures, disposed in parallel in an X direction on the substrate and crossing the word line sets;   a plurality of spacers, disposed in parallel in the X direction on sidewalls of the bit-line structures and comprising silicon oxide;   a plurality of capacitors, respectively disposed at two terminals of a long side of each of the active areas; and   a plurality of capacitor contacts, respectively located between the capacitors and the active areas.   
     
     
         2 . The DRAM according to  claim 1 , wherein each of the spacers comprises a first spacer and a second spacer, and the first spacer is located between the bit-line structure and the second spacer. 
     
     
         3 . The DRAM according to  claim 2 , wherein the first spacers comprise silicon nitride, and the second spacers comprise silicon oxide. 
     
     
         4 . The DRAM according to  claim 1 , further comprising a plurality of dielectric layers respectively located between the capacitor contacts and comprising silicon nitride. 
     
     
         5 . The DRAM according to  claim 1 , wherein each of the word line sets comprises two buried word lines. 
     
     
         6 . The DRAM according to  claim 5 , wherein one of the capacitor contacts covers a part of a top surface of the active area and a part of a top surface of one of the two buried word lines. 
     
     
         7 . The DRAM according to  claim 1 , wherein each of the capacitor contacts is a composite structure comprising a conductive layer, a metal silicide layer and a metal layer. 
     
     
         8 . The DRAM according to  claim 1 , wherein each of the capacitor contacts has a bottom width and a top width, and the bottom width is greater than or equal to the top width. 
     
     
         9 . The DRAM according to  claim 1 , wherein the active areas of two adjacent columns are disposed in a mirror manner. 
     
     
         10 . A method of manufacturing a DRAM, comprising:
 forming a plurality of isolation structures in a substrate to divide the substrate into a plurality of active areas, wherein the active areas are configured in a shape of band and arranged in an array;   forming a plurality of word line sets in the substrate, wherein the word line sets extend in a Y direction and pass through the isolation structures and the active areas to divide the substrate into a plurality of a plurality of first areas and a plurality of second areas, the first areas and the second areas are alternately arranged in an X direction, and the word line sets are located in the first areas;   forming a plurality of bit-line structures on the substrate, wherein the bit-line structures extend in the X direction and cross the word line sets;   forming a plurality of spacers respectively on sidewalls of the bit-line structures;   forming a plurality of conductive layers on the substrate in the second areas;   forming a plurality of first dielectric layers on the substrate in the first areas, wherein top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers;   forming a plurality of second dielectric layers respectively in the conductive layers, wherein each of the second dielectric layers divides the corresponding conductive layer into two conductive posts and a material of the first dielectric layers is the same as a material of the second dielectric layers; and   forming a plurality of capacitors respectively on the conductive posts.   
     
     
         11 . The method according to  claim 10 , wherein the material of the first dielectric layers comprises silicon nitride, and the material of the second dielectric layers comprises silicon nitride. 
     
     
         12 . The method according to  claim 10 , wherein a method of forming the first dielectric layers comprises:
 forming a conductive material on the substrate between each two bit-line structures;   removing a part of the conductive material to form a plurality of openings in the conductive material, wherein the openings expose surfaces of the substrate in the first areas and divide the conductive material into two conductive layers;   filling a first dielectric material in the openings.   
     
     
         13 . The method according to  claim 10 , wherein the second dielectric layers respectively correspond to the isolation structures in the substrate in the second areas to electrically isolate each two adjacent conductive posts from each other. 
     
     
         14 . The method according to  claim 10 , wherein each of the spacers comprises a first spacer and a second spacer, and the first spacer is located between the bit-line structure and the second spacer, and the first spacers comprise silicon nitride, and the second spacers comprise silicon oxide. 
     
     
         15 . The method according to  claim 10 , wherein a method of forming the second dielectric layers comprises:
 forming a third dielectric layer conformally on the conductive layer and the first dielectric layers, wherein a top surface of the third dielectric layer is a continuous concave-convex structure;   performing an etching process to blanketly remove the third dielectric layer and the conductive layers below the third dielectric layer by using the third dielectric layer with the continuous concave-convex structure, so as to form a plurality of openings exposing the isolation structures in the second areas; and   filling a second dielectric material in the openings.   
     
     
         16 . The method according to  claim 10 , wherein each of the word line sets comprises two buried word lines. 
     
     
         17 . The method according to  claim 16 , wherein each of the conductive posts is a capacitor contact covering a part of a top surface of the active area and a part of a top surface of one of the two buried word lines. 
     
     
         18 . The method according to  claim 17 , wherein each of the capacitor contacts has a bottom width and a top width, and the bottom width is greater than or equal to the top width. 
     
     
         19 . The method according to  claim 17 , wherein each of the capacitor contacts is a composite structure comprising a conductive layer, a metal silicide layer and a metal layer. 
     
     
         20 . The method according to  claim 10 , wherein the active areas of two adjacent columns are disposed in a mirror manner.