Display system and method for forming an output buffer of a source driver

Abstract

A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.

What is claimed is: 
     
         1 . A display system, comprising:
 a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines;   a gate driver providing a plurality of gate signals to the plurality of gate lines;   a source driver providing a plurality of image signals to the plurality of source lines, wherein the source driver comprises an output buffer, wherein the output buffer comprises a transistor, and wherein the transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.   
     
     
         2 . The display system as claimed in  claim 1 , wherein the source driver comprises:
 a shift register receiving and processing an image signal and configured to provide a plurality of shift signals;   a data latch receiving and processing the plurality of shift signals and configured to provide a plurality of latched signals;   a level shifter receiving and processing the plurality of latched signals and configured to provide a plurality of converted signals; and   a digital-to-analog converter (DAC) receiving and processing the plurality of converted signals and configured to provide a plurality of analog signals,   wherein the output buffer receiving and processing the plurality of analog signals is configured to provide the plurality of image signals.   
     
     
         3 . The display system as claimed in  claim 1 , wherein the threshold voltage (Vt) of the transistor device is equal to or less than about 0.5 volts (V). 
     
     
         4 . The display system as claimed in  claim 1 , wherein the threshold voltage (Vt) of the transistor device is equal to or less than about 0 volts (V). 
     
     
         5 . The display system as claimed in  claim 1 , wherein the transistor device includes an N-type metal-oxide-semiconductor field effect transistor (NMOS) or a P-type metal-oxide-semiconductor field effect transistor (PMOS). 
     
     
         6 . The display system as claimed in  claim 1 , wherein the transistor device comprises a lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS) or a double diffused drain metal-oxide-semiconductor field effect transistor (DDDMOS). 
     
     
         7 . The display system as claimed in  claim 1 , wherein the N-type metal-oxide-semiconductor field effect transistor comprises a channel region, and the channel region is N-type. 
     
     
         8 . The display system as claimed in  claim 1 , wherein the P-type metal-oxide-semiconductor field effect transistor comprises a channel region, and the channel region is P-type. 
     
     
         9 . A display system, comprising:
 a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines;   a gate driver providing a plurality of gate signals to the plurality of gate lines;   a source driver providing a plurality of image signals to the plurality of source lines, a source driver providing a plurality of image signals to the plurality of source lines, wherein the source driver comprises an output buffer, wherein the output buffer comprises a transistor, and wherein the threshold voltage (Vt) of the transistor device is equal to or less than about 0.5 volts (V) or equal to or less than about 0 volts (V).   
     
     
         10 . The display system as claimed in  claim 9 , wherein the transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device. 
     
     
         11 . The display system as claimed in  claim 9 , further comprising:
 a shift register receiving and processing an image signal and configured to provide a plurality of shift signals;   a data latch receiving and processing the plurality of shift signals and configured to provide a plurality of latched signals;   a level shifter receiving and processing the plurality of latched signals and configured to provide a plurality of converted signals; and   a digital-to-analog converter (DAC) receiving and processing the plurality of converted signals and configured to provide a plurality of analog signals,   wherein the output buffer receiving and processing the plurality of analog signals and configured to provide the plurality of image signals.   
     
     
         12 . The display system as claimed in  claim 9 , wherein the transistor device includes an N-type metal-oxide-semiconductor field effect transistor (NMOS) or a P-type metal-oxide-semiconductor field effect transistor (PMOS). 
     
     
         13 . The display system as claimed in  claim 9 , wherein the transistor device comprises a lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS) or a double diffused drain metal-oxide-semiconductor field effect transistor (DDDMOS). 
     
     
         14 . The display system as claimed in  claim 9 , wherein the N-type metal-oxide-semiconductor field effect transistor comprises a channel region, and the channel region is N-type. 
     
     
         15 . The display system as claimed in  claim 9 , wherein the P-type metal-oxide-semiconductor field effect transistor comprises a channel region, and the channel region is P-type. 
     
     
         16 . The method for forming an output buffer of a source driver, comprising:
 providing a P-type substrate;   forming a high-voltage P-type well doped region in the P-type substrate and two high-voltage N-type well doped regions respective on opposite sides of the high-voltage P-type well doped region;   forming a gate structure on the P-type substrate, wherein the gate structure entirely covers the P-type high-voltage well doped region and covers a portion of the high-voltage N-type well doped regions;   performing a first threshold voltage adjusting implantation process on a portion of the high-voltage P-type well doped region close to a surface of the P-type substrate; and   performing a second device threshold voltage adjusting implantation process on the portion of the high-voltage P-type well doped region close to the surface of the P-type substrate, so that the threshold voltage (Vt) of the output buffer is adjusted equal to or less than about 0.5 volts (V).   
     
     
         17 . The method for forming an output buffer of a source driver as claimed in  claim 16 , wherein dopants implanted by the first device threshold voltage adjusting implantation process have the same conductive type as dopants implanted by the second device threshold voltage adjusting implantation process. 
     
     
         18 . The method for forming an output buffer of a source driver as claimed in  claim 16 , wherein dopants implanted by the first device threshold voltage adjusting implantation process have opposite conductive types to dopants implanted by the second device threshold voltage adjusting implantation process. 
     
     
         19 . The method for forming an output buffer of a source driver as claimed in  claim 16 , wherein the second device threshold voltage adjusting implantation process is performed through a mask, wherein the mask has an opening to expose the portion of the high-voltage P-type well doped region only. 
     
     
         20 . The method for forming an output buffer of a source driver as claimed in  claim 16 , further comprising:
 forming the plurality of N-type heavily doped regions on the high-voltage N-type well doped region after performing the first device threshold voltage adjusting implantation process and the second device threshold voltage adjusting implantation process.