Dynamically Controlling Cache Size To Maximize Energy Efficiency

Abstract

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a first domain including a plurality of cores to independently execute instructions;   a second domain including at least one graphics engine;   a cache memory coupled to the plurality of cores and including a plurality of partitions; and   a power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.