Pixel array substrate and organic light-emitting diode display

Abstract

A pixel array substrate includes a first substrate, pixel units, data lines, scan lines, constant voltage lines, a constant voltage source, a constant voltage pad, and a conductive pattern. The first substrate has pixel regions and a peripheral region surrounding the pixel regions. The conductive pattern includes conductive lines interlaced with each other to form a net and a conductive frame that surrounds and is electrically coupled to the conductive lines. The conductive frame is in electrical contact with the constant voltage pad within the peripheral region. Each pixel region is defined by two adjacent scan lines and two adjacent data lines. A portion of one of the constant voltage lines located completely within each of the pixel regions is in electrical contact with one of the conductive lines within the pixel region. An OLED display including the pixel array substrate and another OLED are also provided.

What is claimed is: 
     
         1 . A pixel array substrate comprising:
 a first substrate having a plurality of pixel regions arranged in an array and a peripheral region surrounding the pixel regions;   a plurality of pixel units located in the pixel regions, each of the pixel units comprising:
 a switch transistor having an input electrode, a control electrode, and an output electrode; 
 a driver transistor having an input electrode, a control electrode, and an output electrode, wherein the output electrode of the switch transistor is electrically coupled to the control electrode of the driver transistor; and 
 a pixel electrode electrically coupled to the output electrode of the driver transistor; 
   a plurality of data lines located on the first substrate and electrically coupled to the input electrodes of the switch transistors;   a plurality of scan lines located on the first substrate, interlaced with the data lines, and electrically coupled to the control electrodes of the switch transistors;   a plurality of constant voltage lines located on the first substrate and electrically coupled to the input electrodes of the driver transistors;   a constant voltage source located on the peripheral region of the first substrate, the constant voltage source providing a constant voltage to the constant voltage lines;   a constant voltage pad located on the peripheral region of the first substrate, the constant voltage pad outputting the constant voltage; and   a conductive pattern located on the first substrate, the conductive pattern comprising:   a plurality of conductive lines interlaced with each other to form a net and located on the pixel regions of the first substrate; and   a conductive frame located on the peripheral region of the first substrate and surrounding and electrically coupled to the conductive lines, the conductive frame being in electrical contact with the constant voltage pad within the peripheral region, wherein each of the pixel regions is defined by two adjacent scan lines of the scan lines and two adjacent data lines of the data lines, at least one of the pixel units and a portion of one of the constant voltage lines are located within each of the pixel regions, the portion of the one of the constant voltage lines is in electrical contact with one of the conductive lines of the conductive pattern, the one of the conductive lines is completely located within the each of the pixel regions, and the conductive pattern is in a film layer different from film layers where the output electrodes of the driver transistors, the input electrodes of the driver transistors, the control electrodes of the driver transistors, and the pixel electrodes are located.   
     
     
         2 . The pixel array substrate as recited in  claim 1 , wherein the conductive lines of the conductive pattern and the constant voltage lines are overlapped. 
     
     
         3 . The pixel array substrate as recited in  claim 2 , wherein the conductive lines are divided into a plurality of first conductive lines and a plurality of second conductive lines, the first conductive lines are parallel to extension directions of the constant voltage lines, the second conductive lines are interlaced with the first conductive lines, and the constant voltage lines cover the first conductive lines. 
     
     
         4 . The pixel array substrate as recited in  claim 3 , wherein the second conductive lines are overlapped with the control electrodes of the driver transistors and the data lines. 
     
     
         5 . The pixel array substrate as recited in  claim 1 , wherein the one of the constant voltage lines is overlapped with the control electrode of the driver transistor of the one of the pixel units to constitute a first storage capacitor, the one of the conductive lines is overlapped with the control electrode of the driver transistor of the one of the pixel units to constitute a second storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to constitute a pixel storage capacitor of the one of the pixel units. 
     
     
         6 . The pixel array substrate as recited in  claim 1 , wherein a film layer where the conductive pattern is located is between the first substrate and a film layer where the input electrodes of the driver transistors are located, and the film layer where the input electrodes of the driver transistors are located is between a film layer where the control electrodes of the driver transistors are located and the film layer where the conductive pattern is located. 
     
     
         7 . The pixel array substrate as recited in  claim 1 , further comprising a plurality of light-shielding patterns respectively shielding a plurality of channels of the switch transistors and a plurality of channels of the driver transistors. 
     
     
         8 . The pixel array substrate as claimed in  claim 7 , wherein the light-shielding patterns and the conductive pattern are located in the same film layer.