US2018374949A1PendingUtilityA1

Method for fabricating ldmos with self-aligned body

Assignee: MONOLITHIC POWER SYSTEMS INCPriority: Sep 28, 2016Filed: Aug 29, 2018Published: Dec 27, 2018
Est. expirySep 28, 2036(~10.2 yrs left)· nominal 20-yr term from priority
H10P 50/691H10P 30/22H01L 29/401H01L 29/1095H01L 29/66681H01L 29/4916H01L 29/6656H01L 29/7816H10D 64/516H10D 62/371H10D 62/157H10D 30/0212H10D 64/661H10D 64/256H10D 64/021H10D 64/01H10D 62/393H10D 62/109H10D 30/0285H10D 30/0281H10D 30/021H10D 62/124H10D 62/10H10D 30/65
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Claims

Abstract

A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An LDMOS device fabricated in a semiconductor substrate, comprising:
 a gate oxide region formed atop the semiconductor substrate;   a gate polysilicon region formed on the gate oxide region;   a first body region of a first doping type formed in the semiconductor substrate, wherein the first body region is located at a first side of the gate polysilicon region and adjacent to the surface of the semiconductor substrate;   a second body region of the first doping type formed beneath the first body region;   a source region of a second doping type formed in the first body region;   a drain region of the second doping type formed in the semiconductor substrate and at a second side of the gate polysilicon region; wherein   the gate polysilicon region, the first body region and the second body region are defined by the same mask and are self-aligned.   
     
     
         2 . The LDMOS of  claim 1 , wherein the semiconductor substrate comprises an original substrate of the first doping type and a buried layer of the second doping type formed in the original substrate. 
     
     
         3 . The LDMOS of  claim 2 , wherein the semiconductor substrate further comprises a well of the second doping type formed in the original substrate. 
     
     
         4 . The LDMOS of  claim 2 , wherein the semiconductor substrate further comprises a resurf layer of the first doping type formed above the buried layer and contacting the second body region. 
     
     
         5 . The LDMOS of  claim 1 , wherein the gate oxide region has a thin gate oxide near the first side of the gate polysilicon region and a thicker gate oxide near the second side of the gate polysilicon region. 
     
     
         6 . The LDMOS of  claim 1 , further comprising:
 a pre-metal dielectric layer formed on the semiconductor substrate;   a trench formed in the pre-metal dielectric layer and the first body region, wherein the trench is laterally located in the center of the source region and vertically extends from the surface of the pre-metal dielectric layer towards a depth greater than the maximum junction depth of the source region;   a contact liner deposited on the bottom and at the sidewalls of the trench; and   metal filling in the trench.

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