US2018372809A1PendingUtilityA1

Hall sensor readout circuit, corresponding device and method

Assignee: ST MICROELECTRONICS SRLPriority: Jun 26, 2017Filed: Jun 20, 2018Published: Dec 27, 2018
Est. expiryJun 26, 2037(~10.9 yrs left)· nominal 20-yr term from priority
G01R 33/07G01R 33/0017G01R 33/075G01R 15/202
58
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Hall sensing signals are received in a spinning readout pattern of subsequent readout phases, wherein the pattern is cyclically repeated at a spinning frequency and a polarity of the Hall sensor signals is reversed in two non-adjacent readout phases of the readout pattern. A signal storage circuit includes signal storage capacitors. An accumulation circuit includes accumulation capacitors. A switch network is selectively actuated to couple the signal storage capacitors with the accumulation capacitors synchronously with phases in the spinning readout pattern in subsequent alternating first and second periods. The spinning output is stored with alternating opposite signs on the signal storage capacitors and the Hall sensing signals are stored in the signal storage capacitors and then accumulated on the accumulation capacitors with alternate signs in subsequent periods. The accumulated output signal is then demodulated with a demodulation frequency half the spinning frequency.

Claims

exact text as granted — not AI-modified
1 . A circuit, comprising:
 a spinning circuit configured to receive Hall sensor signals in a spinning readout pattern of subsequent readout phases, the pattern cyclically repeated at a spinning frequency, wherein the spinning circuit is configured for reversing the polarity of the Hall sensor signals in two non-adjacent readout phases in the readout pattern;   a signal storage circuit including a first and a second set of signal storage capacitors;   an accumulation circuit including a set of accumulation capacitors;   a network of switches selectively actuatable to couple the first and second set of signal storage capacitors in the signal storage circuit with the output from the spinning circuit and with the set of accumulation capacitors in the accumulation circuit, wherein switches of the network of switches are actuatable synchronously with the readout phases in the spinning readout pattern in subsequent alternating first and second periods, with the output from the spinning circuit stored with alternating opposite signs in the first and second set of signal storage capacitors and the Hall sensing signal stored in the first and second set of signal storage capacitors accumulated on the accumulation capacitors with alternate signs in subsequent periods; and   a demodulator circuit configured to demodulate a signal output from the accumulation circuit with a demodulation frequency that is half the spinning frequency.   
     
     
         2 . The circuit of  claim 1 , wherein the set of accumulation capacitors in the accumulation circuit are resettable at each period in said subsequent alternating first and second periods. 
     
     
         3 . The circuit of  claim 1 , wherein the set of accumulation capacitors in the accumulation circuit are resettable at intervals of four accumulation phases of the signal from the spinning circuit stored in the first and second set of signal storage capacitors. 
     
     
         4 . The circuit of  claim 1 , wherein the demodulator circuit includes a sample and hold circuit that is actuated to sample the signal output from the accumulation circuit with alternate positive and negative signs and with a sampling frequency corresponding to said spinning frequency. 
     
     
         5 . The circuit of  claim 1 , further including an amplifier circuit couple between the spinning circuit and the signal storage circuit. 
     
     
         6 . The circuit of  claim 1 , further including at least one low-pass filter configured to receive an output from the demodulator circuit and filter out an accumulation circuit offset. 
     
     
         7 . The circuit of  claim 6 , further including a low-pass filter that is at least partly integrated in the demodulator circuit. 
     
     
         8 . The circuit of  claim 1 , further comprising a Hall sensor configured to provide said Hall sensor signals. 
     
     
         9 . A method, comprising:
 receiving Hall sensor signals in a spinning readout pattern of subsequent readout phases, the pattern cyclically repeated at a spinning frequency, by reversing the polarity of the Hall sensor signals in two non-adjacent readout phases in the readout pattern;   storing the Hall sensor signals with said reversed polarity in a first and a second set of signal storage capacitors;   accumulating the stored Hall sensor signals in a set of accumulation capacitors by selectively feeding the Hall sensor signals with said reversed polarity to the first and second set of signal storage capacitors synchronously with the phases in the spinning readout pattern in subsequent alternating first and second periods, and selectively feeding the Hall sensor signals with reversed polarity stored with alternating opposite signs on the first and second set of signal storage capacitors accumulated on the accumulation capacitors with alternate signs in subsequent periods in the subsequent alternating first and second periods;   demodulating an accumulated signal generated by said accumulating with a demodulating frequency half said spinning frequency.   
     
     
         10 . The method of  claim 9 , further comprising resetting the accumulation capacitors at each period in said subsequent alternating first and second periods. 
     
     
         11 . The method of  claim 9 , further comprising resetting the accumulation capacitors at intervals of four accumulation phases of the Hall sensor signal stored in the first and second set of signal storage capacitors.

Join the waitlist — get patent alerts

Track US2018372809A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.