Semiconductor device

Abstract

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor chip having a main surface over which an electrode is formed; and   an interposer having a first main surface over which a first electrode is formed and a second main surface which is opposed to the first main surface and over which a second electrode electrically coupled to the first electrode is formed, and mounted so that a main surface of the semiconductor chip faces the first main surface so that an electrode of the semiconductor chip is coupled to the first electrode,   wherein when a signal is transmitted between the second electrode and the electrode, the signal is shaped by a first wiring pattern having one end coupled to the electrode and other end to which predetermined voltage is supplied.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a second wiring pattern to which the predetermined voltage is supplied and to which the other end of the first wiring pattern is coupled,
 wherein the second wiring pattern has a region opposed to the first wiring pattern.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein the first wiring pattern is formed over a main surface of the semiconductor chip. 
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the interposer has a third wiring pattern electrically coupling the first and second electrodes, and   wherein electric resistivity of the first wiring pattern is smaller than that of the third wiring pattern.   
     
     
         5 . The semiconductor device according to  claim 3 , wherein the semiconductor chip has an equivalent diode element coupled to the first wiring pattern. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the first wiring pattern has a fourth wiring pattern disposed between a first main surface of the interposer and a second main surface of the interposer. 
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein the interposer has a fifth wiring pattern disposed between the first and second main surfaces and whose line width is wider than that of the fourth wiring pattern, and   wherein the first and second electrodes are electrically coupled via the fifth wiring pattern.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein the interposer has a sixth wiring pattern disposed between the first and second main surfaces and whose line width is narrower than that of the fifth wiring pattern. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the interposer has seventh and eighth wiring patterns disposed so as to sandwich the fourth wiring pattern when viewed from the first main surface of the interposer. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the interposer has a ninth wiring pattern disposed so as to overlap the fourth wiring pattern when viewed from the first main surface side of the interposer. 
     
     
         11 . A semiconductor device comprising:
 a first semiconductor chip having a main surface over which an electrode is formed;   a first interposer having a first main surface over which a first electrode is formed, a second main surface which is opposed to the first main surface and over which a second electrode electrically coupled to the first electrode is formed, and a first wiring pattern having one end coupled to the electrode and other end to which predetermined voltage is supplied, and mounted so that a main surface of the first semiconductor chip faces the first main surface so that the electrode of the first semiconductor chip is coupled to the first electrode; and   a substrate having a main surface opposed to the second main surface of the first interposer, a third electrode formed over the main surface, a fourth electrode formed over the main surface, and a second wiring pattern electrically coupling the third and fourth electrodes,   wherein the third electrode is electrically coupled to the second electrode and, when a signal is transmitted between the fourth electrode and the electrode, the signal is shaped by the first wiring pattern.   
     
     
         12 . The semiconductor device according to  claim 11 , further comprising:
 a second semiconductor chip having a main surface over which an electrode is formed; and   a second interposer having a first main surface over which a fifth electrode is formed and a second main surface which is opposed to the first main surface and over which a sixth electrode electrically coupled to the fifth electrode is formed, and mounted so that the main surface of the second semiconductor chip faces the first main surface so that an electrode of the second semiconductor chip is coupled to the fifth electrode,   wherein the second main surface of the second interposer faces the main surface of the substrate, and the sixth electrode of the second interposer is electrically coupled to the fourth electrode, and   wherein the first semiconductor chip has a first circuit amplifying a signal from the electrode, and the second semiconductor chip has a second circuit outputting a serial signal to the electrode.   
     
     
         13 . The semiconductor device according to  claim 12 , further comprising a first package substrate interposed between the substrate and the first interposer and a second package substrate interposed between the substrate and the second interposer,
 wherein the first package substrate has a first main surface opposed to the second main surface of the first interposer, a second main surface opposed to the main surface of the substrate, a seventh electrode formed over the first main surface and coupled to the second electrode, an eighth electrode formed over the second main surface and coupled to the third electrode, and a wiring pattern coupling the seventh and eighth electrodes,   wherein the second package substrate has a first main surface opposed to the second main surface of the second interposer, a second main surface opposed to the main surface of the substrate, a ninth electrode formed over the first main surface and coupled to the fourth electrode, a tenth electrode formed over the second main surface and coupled to the fifth electrode, and a wiring pattern coupling the ninth and tenth electrodes,   wherein the electrode and the first electrode are electrically coupled via a first bump and the electrode and the fifth electrode are electrically coupled via the first bump,   wherein the second and seventh electrodes are electrically coupled via a second bump and the sixth and ninth electrodes are coupled via the second bump,   wherein the eighth and third electrodes are electrically coupled via a third bump and the tenth and fourth electrodes are electrically coupled via a third bump, and   wherein the size of the first bump is smaller than that of the second bump, and the size of the second bump is smaller than that of the third bump.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein a third semiconductor chip is mounted over a first main surface of the first interposer.