US2018366380A1PendingUtilityA1
Semiconductor package including a semiconductor die having redistributed pads
Assignee: INFINEON TECHNOLOGIES AMERICAS CORPPriority: Nov 10, 2005Filed: Aug 23, 2018Published: Dec 20, 2018
Est. expiryNov 10, 2025(expired)· nominal 20-yr term from priority
H10W 90/736H10W 72/07354H10W 72/07336H10W 72/01935H10W 72/952H10W 72/923H10W 72/874H10W 72/856H10W 72/652H10W 72/354H10W 72/347H10W 72/0198H10W 72/073H10W 70/6875H10W 70/682H10W 70/099H10W 90/00H10W 74/137H10W 74/117H10W 74/01H10W 70/614H10W 70/481H10W 70/457H10W 70/65H10W 70/20H10W 70/09H10W 40/778H10W 40/258H10W 40/22H10W 76/13H01L 2224/24227H01L 23/3128H01L 2224/73267H01L 24/83H01L 2924/40407H01L 2224/73153H01L 25/07H01L 2224/05155H01L 2924/01082H01L 23/142H01L 2224/32257H01L 2924/19042H01L 23/4334H01L 2224/33181H01L 2224/2919H01L 24/37H01L 2224/0508H01L 2224/05139H01L 2224/37147H01L 2924/40252H01L 23/492H01L 23/49582H01L 23/3171H01L 23/49562H01L 23/043H01L 2224/0346H01L 2924/0102H01L 24/19H01L 2924/19043H01L 2924/01027H01L 23/3675H01L 23/3736H01L 23/5389H01L 2224/32245H01L 2924/19041H01L 2924/15153H01L 2924/403H01L 2924/01047H01L 24/24H01L 23/49838H01L 2924/15738H01L 2924/01033H01L 2224/05144H01L 2924/0106H01L 2224/92244H01L 24/32H01L 24/05H01L 21/56H01L 2924/15747H01L 2224/83815H01L 2224/05147H01L 2924/13091H01L 24/03H01L 2924/01079
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Claims
Abstract
A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
Claims
exact text as granted — not AI-modified1 . A semiconductor package, comprising:
a semiconductor die including at least one electrode disposed on one major surface thereof, said electrode having a first area; an insulation body disposed around said semiconductor die; a conforming conductive pad being coupled to said at least one electrode and extending over and conforming to a portion of said insulation body; and a passivation body disposed over said conforming conductive pad, said passivation body including at least one opening over said conforming conductive pad such that an exposed portion of said conforming conductive pad is exposed by said opening, wherein said exposed portion has a second area that is larger than said first area of said electrode.
2 . The package of claim 1 , wherein said conforming conductive pad includes a solderable surface.
3 . (canceled)
4 . The package of claim 1 , wherein said passivation body includes solder resist characteristics.
5 . The package of claim 1 , further comprising a conductive clip having a web portion coupled to another major surface of said semiconductor die opposite said one major surface.
6 . The package of claim 5 , wherein said clip includes at least one lead extending from an edge of said web portion and including a connection surface generally coplanar with said conforming conductive pad.
7 . The package of claim 6 , wherein said web portion is coupled to said another major surface by a conductive adhesive body.
8 . The package of claim 7 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy.
9 . The package of claim 1 , further comprising a conductive plate coupled to another major surface of said semiconductor die opposite said one major surface.
10 . The package of claim 9 , wherein said conductive plate is coupled to said another major surface with a conductive adhesive body.
11 . The package of claim 10 , wherein said conductive adhesive body is comprised of either solder or a conductive epoxy.
12 . The package of claim 9 , further comprising a conductive clip having a web portion coupled to said conductive plate.
13 . The package of claim 12 , wherein said conductive clip includes at least one lead extending from an edge of said web portion and including a connection surface generally coplanar with said conforming conductive pad.
14 - 25 . (canceled)
26 . A method for fabricating a semiconductor package, comprising:
coupling a first major surface of a semiconductor die to a metallic body; depositing an insulation body over said semiconductor die; removing a portion of said insulation body to expose at least one electrode of said semiconductor die on a second major surface of said semiconductor die opposite said first surface, said one electrode having a first area; forming a conductive pad on said one electrode and extending over said insulation body; and forming a passivation body over said conductive pad, said passivation body including at least one opening over said conductive pad such that an exposed portion of said conductive pad is exposed by said opening, wherein said exposed portion has a second area that is larger than said first area of said electrode.
27 . The method of claim 26 , wherein said insulation body is photoimageable.
28 . The method of claim 26 , wherein said conductive pad is formed by forming a seed layer of a conductive material on said one electrode and plating a conductive body on said seed layer.
29 . The method of claim 26 , wherein said conductive pad is comprised of copper.
30 . The method of claim 26 , wherein said metallic body is a metallic plate.
31 . The method of claim 26 , wherein said metallic body is a metallic clip.
32 . The method of claim 31 , wherein said clip includes a connection surface that is generally coplanar with said conductive pad.
33 . The method of claim 31 , wherein said metallic clip is cup-shaped.Join the waitlist — get patent alerts
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