Modifying a Circuit Design

Abstract

Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

What is claimed is: 
     
         1 . A method for modifying circuits to optimize the time required to diagnose broken logic, the method comprising:
 detecting, by one or more processors, negative paths for a circuit design based on a circuit timing test of the circuit design, wherein the detection of negatives paths enables the diagnosis of broken logic in early stages of a project;   assigning, by the one or more processors, each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design;   detecting, by one or more processors, a priority of the logic design flaws, the integration design flaws, and the macro design flaws; and assigning each negative path to the logic bucket, the integration bucket, and the macro bucket based on the priority, wherein the priority indicates: that logic design flaws corresponding to the logic bucket are to be resolved prior to the integration design flaws or the macro design flaws, that integration design flaws are to be resolved in parallel with macro design flaws, and that the macro design flaws are to be resolved prior to the integration design flaws in response to detecting a high slew time, wherein the integration design flaws correspond to a wire delay issue or a buffer delay issue and, wherein the macro design flaws correspond to an actual virtual time that exceeds a best case time by a threshold time delay amount;   detecting, by the one or more processors, a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws;   applying, by the one or more processors, the modification to the circuit design to enable manufacturing of an integrated circuit and to correct the integration design flaws in parallel with the macro design flaws based on the detected priority of the logic design flaws, the integration design flaws, and the macro design flaws, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold, and transmit instructions to an automated manufacturing device to manufacture a circuit with fewer negative paths to reduce latency in the circuit.