Field effect transistor which can be biased to achieve a uniform depletion region

Abstract

A Field Effect Transistor includes a channel with one end designated the source and the other end designated the drain. The Field Effect Transistor also includes a means for connecting to said source end of said channel and a means for connecting to said drain end of said channel. A gate is divided into a plurality of segments each insulated from one another. A means for adjusting the bias of each of said segments independently of one another is configured whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor.

I claim: 
     
         1 . A Field Effect Transistor comprising:
 a channel with one end designated as a source end and another end designated as a drain end;   a means for connecting electrically to the source end of the channel;   a means for connecting electrically to the drain end of the channel;   a gate divided into segments each segment insulated from one another;   a means for connecting electrically to the segments either externally or internally;   whereby separate bias voltages are selectable for each of the segments, wherein the separate bias voltages are selectable to avoid pinch-off and to cause a depletion region to tend to uniformity along the channel, the depletion region in the channel is thus reduced, decreasing ohmic losses in the channel.   
     
     
         2 . The Field Effect Transistor of  claim 1  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of an n-type JFET, p-type JFET, and the MESFET in an enhancement mode and in a depletion mode. 
     
     
         3 . The Field Effect Transistor of  claim 1  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of a DIGMOSFET, HIGFET, IGFET, TFET, CNTMOSFET, LDMOS and the CMOSFET in an enhancement mode and in a depletion mode. 
     
     
         4 . The Field Effect Transistor of  claim 1 , wherein the Field Effect Transistor, is from a family of Field Effect Transistors designated as HEMT, EHEMT, DHEMT, PHEMT, CNTFET, TEGFET, MODFET, SDFET, DHFET and the SUPER HFET in an enhancement mode and in a depletion mode. 
     
     
         5 . The Field Effect Transistor of  claim 1  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of MOSFET, NMOSFET and the PMOSFET in an enhancement mode and in a depletion mode. 
     
     
         6 . A field effect transistor comprising:
 a channel with one end designated as the source end and the other end designated as the drain end;   a gate divided into a plurality of segments including at least a first segment and a second segment, wherein the plurality of segments are each insulated from one another;   a plurality of terminals connected electrically to the plurality of segments including at least a first terminal and a second terminal, wherein the first terminal is connected electrically to the first segment and the second terminal is connected electrically to the second segment,   whereby separate bias voltages are selectable for each segment within the plurality of segments, wherein the separate bias voltages are selectable to avoid pinch-off and to cause a depletion region to tend to uniformity along the channel, the depletion region in the channel is thus reduced, decreasing ohmic losses in the channel.   
     
     
         7 . The Field Effect Transistor of  claim 6  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of an n-type JFET, p-type JFET and the MESFET in an enhancement mode and in a depletion mode. 
     
     
         8 . The Field Effect Transistor of  claim 6  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of DIGMOSFET, HIGFET, IGFET, TFET, CNTMOSFET, LDMOS and the CMOSFET in an enhancement mode and in a depletion mode. 
     
     
         9 . The Field Effect Transistor of  claim 6  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of a HEMT, EHEMT, DHEMT, PHEMT, CNTFET, TEGFET, MODFET, SDFET, DHFET and the SUPER HFET in an enhancement mode and in a depletion mode. 
     
     
         10 . The Field Effect Transistor of  claim 6  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of MOSFET, NMOSFET and the PMOSFET in an enhancement mode and in a depletion mode. 
     
     
         11 . A heterojunction field effect transistor (HFET) comprising:
 a channel with one end designated as the source end and the other end designated as the drain end;   a gate divided into a plurality of segments including at least a first segment and a second segment, wherein the plurality of segments are each insulated from one another;   a plurality of terminals connected electrically to the plurality of segments including at least a first terminal and a second terminal, wherein the first terminal is connected electrically to the first segment and the second terminal is connected electrically to the second segment,   whereby separate bias voltages are selectable for each of the segments, wherein the separate bias voltages are selectable to avoid pinch-off and to cause a depletion region to tend to uniformity along the channel, wherein the depletion region in the channel is thus reduced, decreasing ohmic losses in the channel.   
     
     
         12 . The Field Effect Transistor of  claim 11  wherein the Field Effect Transistor, is from a family of Field Effect Transistors consisting of a HEMT, EHEMT, DHEMT, PHEMT, CNTFET, TEGFET, MODFET, SDFET, DHFET and the SUPER HFET in an enhancement mode and in a depletion mode.