Chip package and manufacturing method thereof

Abstract

A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

What is claimed is: 
     
         1 . A chip package, comprising:
 a chip having a sensor, a conductive pad, a top surface, and a bottom surface that is opposite the top surface, wherein the sensor and the conductive pad are located on the top surface;   a redistribution layer located on the bottom surface of the chip and in electrical contact with the conductive pad; and   an encapsulation layer located on the top surface of the chip and covering the sensor and the conductive pad, wherein the encapsulation layer has a flat surface facing away from the chip.   
     
     
         2 . The chip package of  claim 1 , wherein the chip has a through hole, and the conductive pad is in the through hole, and the chip package further comprises:
 an isolation layer located between the chip and the redistribution layer, and located on a sidewall that surrounds the through hole; and   a passivation layer located on the isolation layer and the redistribution layer, wherein the passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening.   
     
     
         3 . The chip package of  claim 2 , further comprising:
 a conductive structure located on the portion of the redistribution layer and protruding from the passivation layer, and having a bottom surface facing away from the redistribution layer; and   a molding compound covering the passivation layer and surrounding the conductive structure, and having a bottom surface facing away from the passivation layer, wherein the bottom surface of the molding compound and the bottom surface of the conductive structure are at the same horizontal level.   
     
     
         4 . The chip package of  claim 2 , wherein the chip has a concave portion that has two adjacent surfaces, and the two surfaces of the concave portion respectively adjoin the sidewall of the through hole and the bottom surface of the chip, and an obtuse angle is formed between the two surfaces of the concave portion. 
     
     
         5 . The chip package of  claim 4 , wherein the sidewall of the through hole, the two surfaces of the concave portion, and the bottom surface of the chip present a step profile, and the redistribution layer extends from the conductive pad to the bottom surface of the chip along the sidewall of the through hole and the two surfaces of the concave portion, thereby presenting a step profile. 
     
     
         6 . The chip package of  claim 1 , wherein a thickness of the encapsulation layer is in a range from 5 μm to 40 μm, and a dielectric constant of the encapsulation layer is greater than 5. 
     
     
         7 . The chip package of  claim 1 , wherein the chip has a lateral surface that adjoins the top surface and the bottom surface, and the conductive pad protrudes from the lateral surface, and the chip package further comprises:
 a molding compound covering the bottom surface and the lateral surface of the chip, and located between the chip and the redistribution layer, and having a through hole, wherein the conductive pad is in the through hole; and   a passivation layer located on the molding compound and the redistribution layer, wherein the passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening.   
     
     
         8 . The chip package of  claim 7 , further comprising:
 a conductive structure located on the portion of the redistribution layer and protruding from the passivation layer, and having a bottom surface facing away from the redistribution layer, wherein the bottom surface of the conductive structure protrudes from the passivation layer or is level with the passivation layer   
     
     
         9 . The chip package of  claim 7 , wherein the through hole and the redistribution layer extend to the encapsulation layer. 
     
     
         10 . The chip package of  claim 7 , wherein the molding compound has a first surface that surrounds the through hole and a second surface that faces away from the bottom surface of the chip, and the first surface is perpendicular to the second surface, and the redistribution layer extends from the conductive pad to the second surface of the molding compound along the first surface of the molding compound. 
     
     
         11 . A manufacturing method of a chip package, comprising:
 forming a temporary bonding layer on a carrier;   forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer;   bonding the carrier to the wafer, wherein the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer;   patterning a bottom surface of the wafer to form a through hole, wherein the conductive pad is exposed through the through hole;   forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole;   forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole;   forming a passivation layer on the isolation layer and the redistribution layer, wherein the passivation layer has an opening, and a portion of the redistribution layer is in the opening; and   removing the temporary bonding layer and the carrier.   
     
     
         12 . The manufacturing method of the chip package of  claim 11 , further comprising:
 forming a conductive structure on the portion of the redistribution layer.   
     
     
         13 . The manufacturing method of the chip package of  claim 12 , further comprising:
 forming a molding compound covering the passivation layer and the conductive structure; and   grinding the molding compound and the conductive structure such that a bottom surface of the molding compound facing away from the passivation layer and a bottom surface of the conductive structure facing away from the redistribution layer are at the same horizontal level.   
     
     
         14 . The manufacturing method of the chip package of  claim 11 , further comprising:
 patterning a bottom surface of the wafer to form a dicing trench, wherein a portion of the wafer is located between the dicing trench and the through hole, and a portion of the passivation layer is in the dicing trench.   
     
     
         15 . The manufacturing method of the chip package of  claim 14 , further comprising:
 cutting the encapsulation layer and the passivation layer along the dicing trench.   
     
     
         16 . The manufacturing method of the chip package of  claim 11 , wherein patterning the bottom surface of the wafer to form the through hole comprises:
 patterning the bottom surface of the wafer to form a concave portion, wherein the concave portion has two adjacent surfaces; and   patterning one of the two surfaces of the concave portion to form the through hole, wherein the two surfaces of the concave portion are respectively adjoin the sidewall of the through hole and the bottom surface of the wafer.   
     
     
         17 . A manufacturing method of a chip package, comprising:
 forming a temporary bonding layer on a carrier;   forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer;   bonding the carrier to the wafer, wherein the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer;   patterning a bottom surface of the wafer to form a dicing trench, wherein the conductive pad is exposed through the dicing trench;   molding a molding compound to cover the bottom surface of the wafer and the dicing trench;   forming a through hole in the molding compound by laser drilling, wherein the conductive pad is in the through hole;   forming a redistribution layer on the molding compound and the conductive pad that is in the through hole;   forming a passivation layer on the molding compound and the redistribution layer, wherein the passivation layer has an opening, and a portion of the redistribution layer is in the opening; and   removing the temporary bonding layer and the carrier.   
     
     
         18 . The manufacturing method of the chip package of  claim 17 , further comprising:
 forming a conductive structure on the portion of the redistribution layer, wherein a bottom surface of the conductive structure facing away from the redistribution layer protrudes from the passivation layer or is level with the passivation layer.   
     
     
         19 . The manufacturing method of the chip package of  claim 17 , further comprising:
 cutting the encapsulation layer, the molding compound, and the passivation layer along the dicing trench.   
     
     
         20 . The manufacturing method of the chip package of  claim 17 , further comprising:
 extending the through hole to the encapsulation layer by laser drilling; and   forming the redistribution layer on the encapsulation layer that is in the through hole.