Multi-chip semiconductor apparatus

Abstract

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.

What is claimed is: 
     
         1 . A method of testing a multi-chip package having a first semiconductor chip with an externally accessible probe pad and a second semiconductor chip arranged under the first semiconductor chip, the method comprising:
 receiving a first test information via the probe pad of the first semiconductor chip, the first test information being provided to a first memory cell block of the first semiconductor chip;   transmitting a second test information from the first memory cell block of the first semiconductor chip via the probe pad of the first semiconductor chip;   receiving a third test information via the probe pad, the bump pad of the first semiconductor chip, the first TSV of the first semiconductor chip, a second TSV of the second semiconductor chip and a bump pad, a probe pad of the second semiconductor chip, the third test information being provided to a second memory cell block of the second semiconductor chip; and   transmitting a fourth test information from the second memory cell block of the second semiconductor chip via the probe pad, the bump pad of the second semiconductor chip, the second TSV of the second semiconductor chip, the first TSV of the first semiconductor chip and the bump pad, the probe pad of the first semiconductor chip.   
     
     
         2 . The method of  claim 1 , wherein the second memory cell block of in the second semiconductor chip is enabled in response to a corresponding chip select signal prior to the transmitting and receiving test information to and from the second memory cell block. 
     
     
         3 . A method of testing a multi-chip package having a plurality of semiconductor chips, each of the semiconductor chips including a through-silicon via (TSV) formed through the semiconductor chip, a probe pad formed at least one of a first surface and a second surface of the semiconductor chip, an internal circuit formed in the semiconductor chip, bump pads electrically connected to both ends of the TSV, and a plurality of connecting portions electrically connected between the TSV and the probe pad, between the probe pad and the internal circuit, between the internal circuit and the TSV, and between the TSV and at least one of the bump pads, the semiconductor chips being electrically connected by a bump which positioned between the bump pads, the method comprising:
 packaging the plurality of the semiconductor chips which are stacked, to be exposed a selected probe pad; and   serving a signal by the exposed probe pad thereby performing a probe test,   wherein the signal is transmitted to other semiconductor chips through the connecting portions, the TSV and the bump.   
     
     
         4 . The method according to  claim 3 , wherein each of the semiconductor chips includes a memory cell block receiving a chip select signal. 
     
     
         5 . The method according to  claim 4 , wherein the probe test is performed on the semiconductor chip including the memory cell block receiving an enabled chip select signal. 
     
     
         6 . The method according to  claim 4 , wherein the signal serving the exposed probe pad passes through the memory cell block receiving the enabled chip select signal and does not pass through the memory cell block receiving a disabled chip select signal. 
     
     
         7 . The method according to  claim 3 , wherein the selected probe is pad is positioned at an uppermost semiconductor chip of the plurality of the semiconductor chips.