US2018358276A1PendingUtilityA1
Semiconductor device package
Assignee: ADVANCED SEMICONDUCTOR ENGPriority: Nov 19, 2015Filed: Aug 21, 2018Published: Dec 13, 2018
Est. expiryNov 19, 2035(~9.3 yrs left)· nominal 20-yr term from priority
H10P 58/00H10P 54/00H10W 90/736H10W 90/00H10W 74/124H10W 74/111H10W 74/014H10W 72/9413H10W 72/07337H10W 72/874H10W 72/241H10W 72/0198H10W 72/073H10W 70/682H10W 70/421H10W 70/099H10W 70/60H10W 90/811H10W 74/127H10W 74/40H10W 70/6875H10W 70/614H10W 70/479H10W 70/458H10W 70/457H10W 70/424H10W 70/69H10W 70/68H10W 70/20H10W 70/09H10W 42/121H10W 74/114H01L 21/786H01L 25/074H01L 23/3121H01L 2224/97H01L 2224/32257H01L 24/25H01L 23/14H01L 2224/73267H01L 24/97H01L 21/561H01L 23/142H01L 23/13H01L 2224/12105H01L 2224/8385H01L 23/562H01L 23/49861H01L 2224/83H01L 24/24H01L 2224/32245H01L 23/49586H01L 23/49582H01L 23/3142H01L 2924/15153H01L 23/49548H01L 23/492H01L 2224/24247H01L 23/315H01L 2224/04105H01L 23/29H01L 2224/92244H01L 23/3107H01L 23/5389H01L 23/49541H01L 2224/2518H01L 21/78H01L 24/19H01L 23/49575
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Claims
Abstract
A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device package, comprising:
a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.
2 . The semiconductor device package of claim 1 , wherein at least one corner of the conductive base is smoothed.
3 . The semiconductor device package of claim 2 , wherein the first insulating material surrounds the at least one corner of the conductive base.
4 . The semiconductor device package of claim 1 , further comprising a second insulating material disposed on the bottom surface of the conductive base and contacting the first insulating material.
5 . The semiconductor device package of claim 1 , wherein a distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.
6 . The semiconductor device package of claim 1 , wherein a portion of the conductive base defining a sidewall of the cavity further defines an opening.
7 . The semiconductor device package of claim 1 , wherein the conductive base comprises a stepped structure, wherein the stepped structure is filled with the first insulating material.
8 . The semiconductor device package of claim 1 , wherein the conductive base comprises one or more protrusions.
9 . The semiconductor device package of claim 1 , wherein the first insulating material further covers a part of the bottom surface of the conductive base.
10 . The semiconductor device package of claim 1 , further comprising a conductive adhesive layer between the second surface of the semiconductor die and the bottom surface of the cavity, wherein the conductive adhesive layer contacts a portion of the conductive base defining a sidewall of the cavity.
11 . The semiconductor device package of claim 1 , further comprising a second conductive base disposed above the semiconductor die, and a second semiconductor die bonded to the second conductive base.
12 . The semiconductor device package of claim 1 , wherein the first surface of the semiconductor die is below the first surface of the conductive base.
13 . A semiconductor device package, comprising:
a conductive base comprising:
a sidewall;
a first surface and a second surface opposite the first surface; and
a cavity defined from the first surface of the conductive base, the cavity having a bottom surface, a sidewall and a depth; and
a semiconductor die disposed on the bottom surface of the cavity and having a first thickness, wherein at least one corner of the conductive base is smoothed.
14 . The semiconductor device package of claim 13 , further comprising a conductive adhesive layer between the semiconductor die and the bottom surface of the cavity, the conductive adhesive layer having a second thickness,
wherein a sum of the first thickness and the second thickness is less than the depth of the cavity.
15 . The semiconductor device package of claim 13 , wherein a portion of the conductive base defining the sidewall of the cavity further defines an opening.
16 . The semiconductor device package of claim 13 , further comprising a first insulating material, wherein the conductive base comprises a stepped structure, wherein the stepped structure is filled with the first insulating material.
17 . The semiconductor device package of claim 16 , further comprising a solder mask layer disposed over the first insulating material.
18 . The semiconductor device package of claim 13 , wherein the conductive base comprises one or more protrusions.
19 . The semiconductor device package of claim 13 , further comprising a second conductive base disposed above the semiconductor die, and a second semiconductor die bonded to the second conductive base.
20 . The semiconductor device package of claim 13 , further comprising a first insulating material, wherein the first insulating material surrounds the at least one corner of the conductive base.Join the waitlist — get patent alerts
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