Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

Abstract

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a high-k gate dielectric layer disposed over a substrate; and   a metal gate electrode disposed over the high-k gate dielectric layer;   wherein:   the metal gate electrode has a top portion and a bottom portion, the bottom portion being located closer to the high-k gate dielectric layer than the top portion;   the top portion has a first lateral dimension;   the bottom portion has a second lateral dimension; and   the first lateral dimension is no less than the second lateral dimension.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising fluorine-containing particles disposed on an upper surface of the substrate. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the metal gate electrode has a cross-sectional profile that resembles an upside-down trapezoid. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first lateral dimension is greater than the second lateral dimension by at least 20%. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising: a capping layer disposed between the high-k gate dielectric layer and the metal gate electrode. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the capping layer contains a rare earth oxide. 
     
     
         7 . The semiconductor device of  claim 1 , wherein a side surface of the metal gate electrode includes a concave segment or a convex segment in a cross-sectional view. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the side surface of the metal gate electrode includes both the concave segment and the convex segment in the cross-sectional view. 
     
     
         9 . The semiconductor device of  claim 1 , wherein a side surface of the metal gate electrode includes a rounded profile in a cross-sectional view. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the metal gate electrode has more sloped side surfaces than the high-k gate dielectric layer. 
     
     
         11 . The semiconductor device of  claim 1 , wherein:
 the top portion has a first cross-sectional profile that resembles a first rectangle;   the bottom portion has a second cross-sectional profile that resembles a second rectangle; and   the first rectangle is wider than the second rectangle.   
     
     
         12 . The semiconductor device of  claim 1 , wherein:
 the top portion has a first cross-sectional profile that resembles a first trapezoid;   the bottom portion has a second cross-sectional profile that resembles a second trapezoid; and   the first trapezoid is wider than the second trapezoid.   
     
     
         13 . The semiconductor device of  claim 1 , wherein the metal gate electrode further includes a middle portion disposed between the top portion and the bottom portion, wherein the middle portion has a third lateral dimension that is smaller than the first lateral dimension but greater than the second lateral dimension. 
     
     
         14 . A semiconductor device, comprising:
 a gate dielectric layer formed over a substrate;   a gate electrode formed over the gate dielectric layer, wherein the gate electrode has sloped sidewalls; and   fluorine-containing particles disposed over the substrate.   
     
     
         15 . The semiconductor device of  claim 14 , wherein an upper portion of the gate electrode is wider than a bottom portion of the gate electrode by at least 20%. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the gate electrode includes a plurality of segments, and wherein each segment has a wider lateral dimension than another segment disposed therebelow. 
     
     
         17 . The semiconductor device of  claim 14 , wherein the gate dielectric layer contains a high-k gate dielectric material, and wherein the gate electrode contains one or more metal materials, and wherein the semiconductor device further comprises: a capping layer disposed between the gate dielectric layer and the gate electrode, wherein the capping layer contains LaO x , GdO x , DyO x , or ErO x . 
     
     
         18 . The semiconductor device of  claim 14 , wherein sidewalls of the gate dielectric layer are sloped differently than the sidewalls of the gate electrode. 
     
     
         19 . The semiconductor device of  claim 14 , wherein at least a portion of the sloped sidewalls of the gate electrode has a curved, concave, or convex cross-sectional profile. 
     
     
         20 . A semiconductor device, comprising:
 a gate dielectric layer located over a substrate, wherein the gate dielectric layer includes a material having a dielectric constant that is greater than a dielectric constant of SiO 2 ;   a capping layer located over the gate dielectric layer, wherein the capping layer includes a rare earth oxide material;   a gate electrode located over the capping layer, wherein the gate electrode includes one or more metal material, wherein an upper portion of the gate electrode is at least as wide as a lower portion of the gate electrode; and   fluorine-containing particles disposed over the substrate.