Silicon Interposer Sndwich Structure for ESD, EMI, and EMC Shielding and Protection
Abstract
A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.
Claims
exact text as granted — not AI-modified1 - 13 . (canceled)
14 . In a process for providing Electrostatic Discharge, Electromagnetic Interference, and Electromagnetic Conductivity shielding or protection for an integrated circuit electronic device wherein said device is positioned in a cage comprising an interposer sandwich structure comprising a too interposer and a bottom interposer enclosing said device, wherein said interposers are selected from silicon interposers, ceramic interposers and polymeric interposers and combinations thereof;
said interposer sandwich structure including an attaching structure for attaching said device to said bottom interposer, and an interconnection structure connecting said top interposer to said bottom interposer; said top interposer connected to a chip carrier, and includes a blanket metal coating on at least one of the bottom or top surfaces of said top interposer, and further comprises connections to said chip carrier; comprising providing a plurality of said devices connected to said bottom interposer wherein said top interposer is operatively associated with less than all of said devices to provide selective functional isolation of said devices for shielding for maximum miniaturization; wherein said attaching structure for attaching said device to said bottom interposer comprises small solder bumps that provide electrical connections to an electrical around or bias and said interconnection structure comprises bumps selected from copper bumps or large solder bumps; wherein said process further comprises a thermal interface material operatively associated with said devices to provide rapid heat dissipation from said devices.
15 - 24 . (canceled)
25 . The process of claim 14 wherein said interposer is selected from silicon interposers.Join the waitlist — get patent alerts
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