Implementing a Service Using Plural Acceleration Components

Abstract

A data processing system is described herein that includes two or more software-driven host components that collectively provide a software plane. The data processing system further includes two or more hardware acceleration components that collectively provide a hardware acceleration plane. The hardware acceleration plane implements one or more services, including at least one multi-component service. The multi-component service has plural parts, and is implemented on a collection of two or more hardware acceleration components, where each hardware acceleration component in the collection implements a corresponding part of the multi-component service. Each hardware acceleration component in the collection is configured to interact with other hardware acceleration components in the collection without involvement from any host component. A function parsing component is also described herein that determines a manner of parsing a function into the plural parts of the multi-component service.

1 - 15 . (canceled) 
     
     
         16 . A hardware acceleration component, comprising:
 access to a local link for communicating with a local host component associated with the hardware acceleration component, the local host component using one or more central processing units to execute machine-readable instructions;   logic configured to receive setup information that identifies a connection of the hardware acceleration component to other hardware acceleration components in a collection of hardware acceleration components that perform a multi-component service;   logic configured to receive input information from one or more upstream hardware acceleration components in the collection, or from a requesting host component that has requested use of the multi-component service;   logic configured to perform a part of the multi-component service to provide output information, based on the input information that is received; and   logic configured to provide the output information to one or more downstream components in the collection, or to the requesting host component,   the hardware acceleration component performing its processing without involvement by a requesting host component, and without the requesting host component being aware that it has requested a multi-component service.   
     
     
         17 . The hardware acceleration component of  claim 16 , wherein the collection of hardware acceleration components is structured as a ring. 
     
     
         18 . The hardware acceleration component of  claim 16 , wherein the collection of hardware acceleration components is structured to include parallel paths to accommodate parallel processing. 
     
     
         19 . The hardware acceleration component of  claim 16 , wherein the requesting host component accesses the collection of hardware acceleration components via a head component. 
     
     
         20 . The hardware acceleration component of  claim 16 , wherein the hardware acceleration component is a field-programmable gate array (FPGA) device. 
     
     
         21 . The hardware acceleration component of  claim 16 , the local link being a Peripheral Component Interconnect Express (PCIe) link. 
     
     
         22 . The hardware acceleration component of  claim 16 , further comprising a bridge configured to couple the hardware acceleration component to a network interface controller and a switch. 
     
     
         23 . The hardware acceleration component of  claim 22 , the switch being a top-of-rack switch. 
     
     
         24 . The hardware acceleration component of  claim 23 , further comprising the network interface controller. 
     
     
         25 . A method comprising:
 receiving setup information for a hardware acceleration component, the setup information specifying a connection of the hardware acceleration component to a downstream hardware acceleration component;   receiving input information for processing;   performing a first part of a multi-component service using the hardware acceleration component to obtain output information; and   sending the output information to the downstream hardware acceleration component, wherein the downstream hardware acceleration component performs another part of the multi-component service.   
     
     
         26 . The method of  claim 25 , performed entirely by the hardware acceleration component. 
     
     
         27 . The method of  claim 25 , the setup information specifying an upstream hardware acceleration component that sends the input information to the hardware acceleration component. 
     
     
         28 . The method of  claim 25 , further comprising:
 partially reconfiguring the hardware acceleration component to perform the first part of the multi-component service.   
     
     
         29 . The method of  claim 28 , the partially reconfiguring comprising:
 receiving a configuration stream specifying logic for performing the first part of the multi-component service; and   reconfiguring a subset of tiles of the hardware acceleration component using the logic specified by the configuration stream while other tiles of the hardware acceleration component remain available for reconfiguration.   
     
     
         30 . A server unit component comprising:
 a processing unit;   a hardware acceleration component; and   a local link connecting the processing unit to the hardware acceleration component,   the hardware acceleration component being configured to:
 receive input information from the processing unit over the local link; 
 perform part of a multi-component service on the input information to obtain an intermediate output result; 
 invoke another hardware acceleration component to perform another part of the multi-component service on the intermediate output result to obtain a final output result; 
 receive the final output result from the another hardware acceleration component; and 
 provide the final output result to the processing unit. 
   
     
     
         31 . The server unit component of  claim 30 , wherein the processing unit, the hardware acceleration component, and the local link are housed together as a single physical unit. 
     
     
         32 . The server unit component of  claim 30 , further comprising a network interface controller provided separately from the hardware acceleration component. 
     
     
         33 . The server unit component of  claim 30 , the hardware acceleration component comprising a network interface controller. 
     
     
         34 . The server unit component of  claim 33 , the hardware acceleration component comprising a multi-port switch configured to route packets between the network interface controller and a top-of-rack switch. 
     
     
         35 . The server unit component of  claim 34 , the multi-port switch being further configured to route the packets between the network interface controller and a local port associated with the hardware acceleration component.