Apparatus and method for hardware-accelerated packet processing

Abstract

Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.

1 . (canceled) 
     
     
         2 . A hardware switch comprising:
 ingress ports for receiving a plurality of packet streams;   a control interface to communicate with a control device; and   a data plane interface to communicate with one or more data plane processors, wherein the hardware switch is configured to provide capability information to the control interface and to receive, over the control interface, indications of which packet streams, of the plurality of packet streams, are designated to be processed by the hardware switch based on the capability information.   
     
     
         3 . The hardware switch of  claim 2 , wherein the capability information includes quality of service capabilities. 
     
     
         4 . The hardware switch of  claim 2 , wherein the capability information includes information as to whether the switch supports hardware accelerator capabilities. 
     
     
         5 . The hardware switch of  claim 2 , wherein the hardware switch is configured with a routing rule to steer traffic targeted for a Service Function Forwarder (SFF) instance executing on the one or more data plane processors. 
     
     
         6 . The hardware switch of  claim 2 , further including one or more flow tables to store rules for routing packet streams. 
     
     
         7 . The hardware switch of  claim 6 , wherein the hardware switch is further configured to store extended flow tables in random access memory (RAM). 
     
     
         8 . The hardware switch of  claim 2 , wherein the hardware switch is further configured to receive a hardware hint to instruct the hardware switch to direct packets to a target processing core for processing a corresponding packet stream. 
     
     
         9 . A control device comprising:
 a switch interface to communicate with one or more hardware switches;   a data plane interface to communicate with one or more data plane processors; and   processing circuitry configured to:   detect characteristics of a plurality of packet streams received at the switch interface, and   distribute at least one of the plurality of packet streams to the one or more hardware switches hardware switches based on the characteristics.   
     
     
         10 . The control device of  claim 9 , wherein the packet streams are distributed such that less-frequently-accessed packet streams are directed to software data plane components and more-frequently-accessed packet streams are directed to one or more hardware switches. 
     
     
         11 . The control device of  claim 9 , wherein the characteristics include whether the packet streams are comprised solely of input/output (I/O) flows and the amount of processing power expected to be used by the packet streams. 
     
     
         12 . The control device of  claim 9 , wherein the processing circuitry is configured to program at least one of the one or more hardware switches with a rule to steer traffic targeted for a Service Function Forwarder (SFF) instance executing on the one or more data plane processors. 
     
     
         13 . The control device of  claim 9 , wherein the processing circuitry is further configured to:
 detect capability information for the one or more hardware switches, and wherein the processing circuitry distributes the plurality of packet streams based at least in part on the capability information for the one or more hardware switches.   
     
     
         14 . The control device of  claim 9 , wherein the processing circuitry is configured to direct simple packet streams to the one or more hardware switches, and wherein the processing circuitry determines whether a respective packet stream of the plurality of packet streams is a simple packet stream based on a number of central processing unit (CPU) machine cycles expected to be used by the respective packet stream. 
     
     
         15 . The control device of  claim 14 , wherein the processing circuitry is configured to detect traffic load data corresponding to the plurality of packet streams, and to direct one or more packet streams to the one or more hardware switches based on the traffic load data. 
     
     
         16 . A system comprising:
 a control device;   a software data plane component to communicate to the control device using a data plane inter face; and   a hardware switch to communicate with the control device over a switch interface, wherein the control device is configured to distribute packet streams between the software data plane component and the hardware switch based on characteristics of the packet streams.   
     
     
         17 . The system of  claim 16 , wherein the software data plane component includes software-defined networking (SDN) element. 
     
     
         18 . The system of  claim 16 , wherein the software data plane component includes a network function virtualization (NFV) component. 
     
     
         19 . The system of  claim 16 , wherein the control device executes on a processing core specific to the control device. 
     
     
         20 . The control device of  claim 16 , wherein the control device functionality is distributed between two or more processing cores.