High-K Dielectric and Method of Manufacture

Abstract

A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO 2 ) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (Hf x Ti 1-x O 2 ) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a substrate;   a hafnium oxide silicate layer over the substrate;   a first hafnium oxide layer over the hafnium oxide silicate layer;   a hafnium titanium oxide layer over the first hafnium oxide layer; and   a second hafnium oxide layer over the hafnium titanium oxide layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the hafnium titanium oxide layer contacts the first hafnium oxide layer and the second hafnium oxide layer. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein a height between a bottom surface of the first hafnium oxide layer and a top surface of the second hafnium oxide layer is between about 5 Å and about 50 Å. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein a height between a bottom surface of the first hafnium oxide layer and a top surface of the second hafnium oxide layer correspond to an equivalent oxide thickness of between 1.6 Å and about 2.2 Å. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the substrate comprises a cylindrical shape, the hafnium oxide silicate layer forming a ring around the cylindrical shape. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the first hafnium oxide layer comprises:
 0.01% (wt/wt) to about 5% (wt/wt) titanium;   0.01% (wt/wt) to about 0.5% (wt/wt) aluminum;   0.01% (wt/wt) to about 1.0% (wt/wt) tantalum, cobalt, copper, carbon, or nitrogen; and   0.01% (wt/wt) to about 2.0% (wt/wt) silicon.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein the hafnium titanium oxide layer comprises:
 0.05% (wt/wt) to about 6% (wt/wt) titanium;   0.01% (wt/wt) to about 0.5% (wt/wt) aluminum;   0.01% (wt/wt) to about 1.0% (wt/wt) tantalum, cobalt, copper, carbon, or nitrogen; and   0.01% (wt/wt) to about 2.0% (wt/wt) silicon.   
     
     
         8 . The semiconductor structure of  claim 1 , wherein the second hafnium oxide layer comprises:
 0.1% (wt/wt) to about 10% (wt/wt) titanium;   0.2% (wt/wt) to about 5.0% (wt/wt) aluminum;   1.0% (wt/wt) to about 2.0% (wt/wt) tantalum, cobalt, copper, carbon, or nitrogen; and   0.05% (wt/wt) to about 5.0% (wt/wt) silicon.   
     
     
         9 . A semiconductor structure comprising:
 a semiconductor substrate;   a hafnium oxide silicate layer directly on the semiconductor substrate;   a first hafnium oxide layer directly contacting the hafnium oxide silicate layer;   a hafnium titanium oxide layer directly contacting the first hafnium oxide layer;   a second hafnium oxide layer directly contacting the hafnium titanium oxide layer, wherein the hafnium oxide silicate layer, the first hafnium oxide layer, the hafnium titanium oxide layer and the second hafnium oxide layer collectively form a composite gate dielectric; and   a gate electrode overlying the composite gate dielectric, wherein the composite gate dielectric is interposed between the gate electrode and the semiconductor substrate.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein a combined thickness of the first hafnium oxide layer, the hafnium titanium oxide layer, and the second hafnium oxide layer is between 9 Å and 90 Å. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the composite gate dielectric are along opposing sidewalls of a portion of the semiconductor substrate. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein the portion comprises a cylindrical shape, and wherein the composite gate dielectric forms a ring around the cylindrical shape. 
     
     
         13 . The semiconductor structure of  claim 9 , wherein the second hafnium oxide layer comprises nitrogen. 
     
     
         14 . The semiconductor structure of  claim 9 , wherein the second hafnium oxide layer comprises tantalum. 
     
     
         15 . The semiconductor structure of  claim 9 , wherein a thickness of the hafnium titanium oxide layer is between 5 Å and 100 Å. 
     
     
         16 . A semiconductor structure comprising:
 a semiconductor substrate;   a metal oxide silicate layer overlying the semiconductor substrate;   a first metal oxide layer overlying the metal oxide silicate layer;   a second metal oxide layer overlying the first metal oxide layer, the second metal oxide layer comprising two different metals;   a third metal oxide layer overlying the second metal oxide layer, wherein a surface of the third metal oxide layer facing away from the semiconductor substrate is denser than a surface of the third metal oxide layer facing the semiconductor substrate; and   a gate electrode overlying the third metal oxide layer.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein the second metal oxide layer comprises:
 0.05% (wt/wt) to about 6% (wt/wt) titanium;   0.01% (wt/wt) to about 0.5% (wt/wt) aluminum;   0.01% (wt/wt) to about 1.0% (wt/wt) tantalum, cobalt, copper, carbon, or nitrogen; and   0.01% (wt/wt) to about 2.0% (wt/wt) silicon.   
     
     
         18 . The semiconductor structure of  claim 16 , wherein the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer are U-shaped. 
     
     
         19 . The semiconductor structure of  claim 16 , wherein the second metal oxide layer comprises nitrogen. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein metal oxide silicate layer comprises hafnium oxide silicate, the first metal oxide layer comprises hafnium oxide, the second metal oxide layer comprises hafnium titanium oxide, and the third metal oxide layer comprises hafnium oxide silicate.