Ic structure including tsv having metal resistant to high temperatures and method of forming same

Abstract

A method of forming an IC structure, including: forming a first plurality of active devices within a first semiconductor layer over a substrate; forming a first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.); forming a second semiconductor layer over the first wiring layer; forming a second plurality of active devices within the second semiconductor layer; and forming a second wiring layer over the second semiconductor layer, the second wiring layer including the first metal having a melting point greater than approximately 1400 degrees Celsius (° C.).

What is claimed is: 
     
         1 . A method of forming an IC structure, comprising:
 forming a first plurality of active devices within a first semiconductor layer over a substrate;   forming a first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.);   forming a second semiconductor layer over the first wiring layer;   forming a second plurality of active devices within the second semiconductor layer; and   forming a second wiring layer over the second semiconductor layer, the second wiring layer including the first metal.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a first through silicon via (TSV) through the second wiring layer and the second semiconductor layer to the first wiring layer;   forming a second TSV to the second wiring layer; and   forming a back-end-of-the-line (BEOL) metallization over the second wiring layer connecting the first TSV and the second TSV.   
     
     
         3 . The method of  claim 2 , wherein the first TSV and the second TSV include copper. 
     
     
         4 . The method of  claim 2 , wherein the second TSV is formed in a staggered formation with respect to the first TSV. 
     
     
         5 . The method of  claim 1 , wherein the second plurality of active devices is formed in a staggered formation with respect to the first plurality of active devices. 
     
     
         6 . The method of  claim 1 , wherein forming the first plurality of active devices includes performing a first anneal to activate each device in the first plurality of devices. 
     
     
         7 . The method of  claim 6 , wherein forming the second plurality of active devices includes performing a second anneal to activate each device in the second plurality of devices. 
     
     
         8 . The method of  claim 1 , further comprising:
 after forming the first wiring layer and before forming the second semiconductor layer, forming a first insulator layer over the first wiring layer and a first crystalline silicon layer over the first insulator layer; and   after forming the second wiring layer, forming a second insulator layer over the second wiring layer and a second crystalline silicon layer over the second insulator layer.   
     
     
         9 . The method of  claim 1 , wherein the first metal includes at least one of: tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, and platinum. 
     
     
         10 . The method of  claim 1 , further comprising:
 after forming the first plurality of active devices and before forming the first wiring layer, forming a first plurality of vias within the first semiconductor layer such that each via of the first plurality of vias connects a portion of a respective active device of the first plurality of active devices to the first wiring layer; and   after forming the second plurality of active devices and before forming the second wiring layer, forming a second plurality of vias within the second semiconductor layer such that each via of the second plurality of vias connects a portion of a respective active device of the second plurality of active devices to the second wiring layer,   wherein each via of the first plurality of vias and the second plurality of vias includes a second metal having a melting point greater than approximately 1400 degrees Celsius (° C.).   
     
     
         11 . The method of  claim 10 , wherein the second metal includes at least one of: tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, and platinum. 
     
     
         12 . A method of forming an IC structure, comprising:
 forming a first plurality of devices within a first semiconductor layer over a substrate;   performing a first anneal to activate each device in the first plurality of devices; forming a first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.);   forming a second semiconductor layer over the first wiring layer;   forming a second plurality of devices within the second semiconductor layer;   performing a second anneal to activate each device in the second plurality of devices; and   forming a second wiring layer over the second semiconductor layer, the second wiring layer including the first metal.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming a first through silicon via (TSV) through the second wiring layer and the second semiconductor layer to the first wiring layer;   forming a second TSV to the second wiring layer; and   forming a back-end-of-the-line (BEOL) metallization over the second wiring layer connecting the first TSV and the second TSV.   
     
     
         14 . The method of  claim 13 , wherein the second TSV is formed in a staggered formation with respect to the first TSV. 
     
     
         15 . The method of  claim 12 , wherein the second plurality of devices is formed in a staggered formation with respect to the first plurality of devices. 
     
     
         16 . The method of  claim 12 , further comprising:
 after forming the first wiring layer and before forming the second semiconductor layer, forming a first insulator layer over the first wiring layer and a first crystalline silicon layer over the first insulator layer; and   after forming the second wiring layer, forming a second insulator layer over the second wiring layer and a second crystalline silicon layer over the second insulator layer.   
     
     
         17 . The method of  claim 12 , wherein the first metal includes at least one of: tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, and platinum. 
     
     
         18 . The method of  claim 12 , further comprising:
 after forming the first plurality of active devices and before forming the first wiring layer, forming a first plurality of vias within the first semiconductor layer such that each via of the first plurality of vias connects a portion of a respective device of the first plurality of devices to the first wiring layer; and   after forming the second plurality of active devices and before forming the second wiring layer, forming a second plurality of vias within the second semiconductor layer such that each via of the second plurality of vias connects a portion of a respective device of the second plurality of devices to the second wiring layer,   wherein each via of the first plurality of vias and the second plurality of vias includes a second metal having a melting point greater than approximately 1400 degrees Celsius (° C.).   
     
     
         19 . The method of  claim 18 , wherein the second metal includes at least one of: tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, and platinum. 
     
     
         20 . A method of forming an IC structure, comprising:
 forming a first plurality of devices within a first semiconductor layer over a substrate;   forming a first plurality of vias within the first semiconductor layer such that each via of the first plurality of vias connects a portion of a respective device of the first plurality of devices to a first wiring layer and wherein each via of the first plurality of vias includes a second metal having a melting point greater than approximately 1400 degrees Celsius (° C.);   forming the first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.);   performing a first anneal to activate each device in the first plurality of devices;   forming a first insulator layer over the first wiring layer and a first crystalline silicon layer over the first insulator layer;   forming a second semiconductor layer over the first crystalline silicon layer;   forming a second plurality of devices within the second semiconductor layer;   forming a second plurality of vias within the second semiconductor layer such that each via of the second plurality of vias connects a portion of a respective device of the second plurality of devices to a second wiring layer and wherein each via of the second plurality of vias includes the second metal;   forming the second wiring layer over the second semiconductor layer, the second wiring layer including the first metal;   performing a second anneal to activate each device in the second plurality of devices; and   forming a second insulator layer over the second wiring layer and a second crystalline silicon layer over the second insulator layer.