Field effect transistor and method of fabricating the same

Abstract

Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

What is claimed is: 
     
         1 . A field effect transistor, comprising:
 a substrate including an active fin;   a gate insulating layer covering the active fin, the gate insulating layer formed of at least one high-k dielectric material;   a gate pattern on the gate insulating layer to cross the active fin;   gate spacers at sidewalls of the gate pattern to cross the active fin;   a source electrode on the active fin at one side of the gate pattern;   a drain electrode on the active fin at another side of the gate pattern; and   silicide patterns on the source and drain electrodes, respectively,   wherein the gate pattern comprises a first gate electrode and a second gate electrode on the first gate electrode, the first gate electrode extending from a region between the second gate electrode and the gate insulating layer to a region between a sidewall of the second gate electrode and the gate spacers, and   wherein the first gate electrode directly contacts inner sidewalls of the gate spacers and a top surface of the gate insulating layer.   
     
     
         2 . The transistor of  claim 1 , wherein the gate insulating layer has a dielectric constant that is smaller than that of the gate insulating layer. 
     
     
         3 . The transistor of  claim 1 , wherein the active fin has a tapered structure a width of which decreases in an upward direction relative to the substrate. 
     
     
         4 . The transistor of  claim 1 , further comprising device isolation patterns positioned in the substrate and extending along a direction parallel to the active fin,
 wherein the device isolation patterns have a top surface lower than a top surface of the active fin.   
     
     
         5 . The transistor of  claim 1 , wherein the gate insulating layer has a single- or multi-layered structure. 
     
     
         6 . The transistor of  claim 1 , wherein the gate insulating layer has a width that is substantially same as a width of the gate pattern. 
     
     
         7 . The transistor of  claim 1 , wherein the source and drain electrodes include a different material than a material of the substrate. 
     
     
         8 . The transistor of  claim 1 , wherein the first gate electrode is formed of one or more metal nitrides and the second gate electrode is formed of one or more metals. 
     
     
         9 . The transistor of  claim 1 , wherein the substrate comprises an NMOS region and a PMOS region, and wherein the source and drain electrodes comprise:
 an epitaxial layer having a tensile strain property in the NMOS region; and   an epitaxial layer having a compressive strain property in the PMOS region.   
     
     
         10 . The transistor of  claim 1 , wherein the active fin comprises a channel region between the source and drain electrodes and below the gate pattern, and
 wherein the gate pattern comprises first portions facing both sidewalls of the channel region and a second portion provided on the channel region to connect the first portions with each other, and   wherein the first portions are thicker than the second portion.   
     
     
         11 . A field effect transistor, comprising:
 a plurality of active patterns extending in a first direction;   device isolation patterns extending in the first direction between the active patterns, the device isolation patterns having a top surface lower than top surfaces of the active patterns;   a gate structure crossing the active patterns and the device isolation patterns and extending in a second direction crossing the first direction;   gate spacers at sidewalls of the gate pattern;   a high-k gate dielectric pattern extending in the first direction below a bottom surface of the gate structure and disposed between the gate spacers;   a source electrode on the active pattern at one side of the gate structure;   a drain electrode on the active pattern at another side of the gate structure; and   silicide patterns on surfaces of the source and drain electrodes, respectively.   
     
     
         12 . The transistor of  claim 11 , wherein the gate spacers have a dielectric constant that is smaller than that of the high-k gate dielectric pattern. 
     
     
         13 . The transistor of  claim 11 , wherein the gate structure comprises a first gate electrode and a second gate electrode on the first gate electrode,
 the first gate electrode extending from a region between a bottom surface of the second gate electrode and the high-k gate dielectric pattern to a region between sidewalls of the second gate electrode and the gate spacers.   
     
     
         14 . The transistor of  claim 13 , wherein the first gate electrode directly contacts inner sidewalls of the gate spacers and a top surface of the high-k gate dielectric pattern. 
     
     
         15 . The transistor of  claim 11 , wherein the first gate electrode is formed of one or more metal nitrides and the second gate electrode is formed of one or more metals. 
     
     
         16 . The transistor of  claim 11 , wherein each of the active patterns comprises a channel region between the source and drain electrodes and below the gate structure, and
 wherein the gate structure comprises first portions facing both sidewalls of the channel region and a second portion provided on the channel region to connect the first portions with each other.   
     
     
         17 . The transistor of  claim 16 , wherein the first portions are thicker than the second portion. 
     
     
         18 . The transistor of  claim 11 , wherein top surfaces of the source and drain electrodes are higher than the bottom surface of the gate structure adjacent the source and drain electrodes, and
 wherein opposite side surfaces of the source and drain electrodes and the gate structure are spaced apart from each other by a substantially uniform distance.   
     
     
         19 . The transistor of  claim 11 , wherein the source and drain electrodes include a different material than a material of the substrate. 
     
     
         20 . The transistor of  claim 11 , wherein the high-k gate dielectric pattern has a substantially same width as a width of the gate structure.