Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

Abstract

A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

What is claimed is: 
     
         1 . A monolithic three-dimensional memory device comprising:
 a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate;   a joint level dielectric material layer overlying the first alternating stack;   a second alternating stack of second insulating layers and second electrically conductive layers located over the joint level dielectric material layer;   an inter-tier memory opening extending through the second alternating stack, the joint level dielectric material layer, and the first alternating stack; and   a memory stack structure located within the inter-tier memory opening and comprising a memory film and a semiconductor channel,   wherein:   the memory film comprises a lower portion located adjacent to the first alternating stack, an upper portion located adjacent to the second alternating stack, and a joint portion located between the lower portion and the upper portion and adjacent to the joint level dielectric material layer;   a tapered outer sidewall of the joint portion of the memory film contacts a tapered sidewall of the joint level dielectric material layer in the memory opening; and   an outer sidewall of the lower portion and an outer sidewall of the upper portion of the memory film are either untapered or have a smaller taper angle than a taper angle of the tapered outer sidewall of the joint portion of the memory film.   
     
     
         2 . The monolithic three-dimensional memory device of  claim 1 , wherein the tapered outer sidewall of the joint portion of the memory film has a uniform taper angle throughout, and the uniform taper angle is in a range from 5 degrees to 45 degrees with respect to a vertical direction that is perpendicular to a top surface of the substrate. 
     
     
         3 . The monolithic three-dimensional memory device of  claim 1 , wherein:
 an annular horizontal surface of the memory film contacts the horizontal bottom surface of the second alternating stack; and   an upper periphery of the tapered outer sidewall of the joint portion of the memory film adjoins an outer periphery of the annular horizontal surface of the memory film.   
     
     
         4 . The monolithic three-dimensional memory device of  claim 3 , wherein the outer sidewall of the upper portion of the memory film extends through the second alternating stack and has a lower periphery that adjoins an inner periphery of the annular horizontal surface of the memory film. 
     
     
         5 . The monolithic three-dimensional memory device of  claim 1 , wherein:
 the outer sidewall of the lower portion of the memory film extends through the first alternating stack and includes an upper periphery that adjoins a lower periphery of the tapered outer sidewall of the joint portion of the memory film; and   a taper angle of the tapered outer sidewall of the joint portion of the memory film with respect to a vertical direction that is perpendicular to a top surface of the substrate is greater than a taper angle of the outer sidewall of the lower portion of the memory film by at least 3 degrees.   
     
     
         6 . The monolithic three-dimensional memory device of  claim 5 , wherein:
 the upper periphery of the outer sidewall of the lower portion of the memory film is located on a surface of the joint level dielectric material layer; and   a lower periphery of the outer sidewall of the lower portion of the memory film adjoins an outer periphery of a bottommost surface of the memory film.   
     
     
         7 . The monolithic three-dimensional memory device of  claim 1 , wherein:
 the memory film comprises a lateral stack of a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer; and   each of the blocking dielectric layer, the charge storage layer, and the tunneling dielectric layer extends continuously through the second alternating stack, the joint level dielectric material layer, and the first alternating stack as a respective continuous material layer.   
     
     
         8 . The monolithic three-dimensional memory device of  claim 1 , wherein:
 a bottom surface of the memory stack structure contacts a doped semiconductor material portion located on, or within, the substrate; and   the semiconductor channel protrudes downward into the doped semiconductor material portion such that a sidewall of the semiconductor channel contacts the doped semiconductor material portion.   
     
     
         9 . The monolithic three-dimensional memory device of  claim 1 , further comprising a backside blocking dielectric layer including vertical portions located between the memory film and each of the first and second electrically conductive layers and horizontal portions contacting each top surface and each bottom surface of the first and second electrically conductive layers, wherein the joint level dielectric material layer contacts a horizontal portion of the backside blocking dielectric layer overlying a topmost one of the first electrically conductive layers. 
     
     
         10 . The monolithic three-dimensional memory device of  claim 1 , wherein:
 the first alternating stack comprises a first terrace region in which each first electrically conductive layer other than a topmost first electrically conductive layer within the first alternating stack laterally extends farther than any overlying first electrically conductive layer within the first alternating stack;   the second alternating stack comprises a second terrace region in which each second electrically conductive layer other than a topmost second electrically conductive layer within the second alternating stack laterally extends farther than any overlying second electrically conductive layer within the second alternating stack;   the first and second terrace regions include stepped surfaces that continuously extend from a bottommost layer within the first alternating stack to a topmost layer within the second alternating stack; and   the support pillar structures extend through the stepped surfaces and through at least one retro-stepped dielectric material portion that overlies the stepped surfaces.   
     
     
         11 . The three-dimensional memory device of  claim 1 , wherein:
 the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;   the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;   the substrate comprises a silicon substrate;   the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;   at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;   the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;   the first and second electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and   the array of monolithic three-dimensional NAND strings comprises:
 a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and 
 a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels. 
   
     
     
         12 . A method of forming a monolithic three-dimensional memory device, comprising:
 forming a first alternating stack of first insulating layers and first spacer material layers over a substrate;   forming a joint level dielectric material layer over the first alternating stack;   forming a first memory opening through the joint level dielectric material layer and the first alternating stack,   forming a tapered sidewall of the joint level dielectric material layer in the first memory opening;   forming a second alternating stack of second insulating layers and second spacer material layers over the joint level dielectric material layer, wherein the first and second spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;   forming an inter-tier memory opening that includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening; and   forming a memory stack structure within the inter-tier memory opening,   
       wherein:
 the memory stack structure comprises a memory film and a semiconductor channel; and 
 a tapered outer sidewall of the memory film is formed directly on the tapered sidewall of the joint level dielectric material layer. 
 
     
     
         13 . The method of  claim 12 , further comprising:
 forming an in-process first memory opening through the joint level dielectric material layer and the first alternating stack, wherein surfaces of the in-process first memory opening include a substantially vertical sidewall of the joint level dielectric material layer; and   forming the tapered sidewall of the joint level dielectric material layer by etching the substantially vertical sidewall of the joint level dielectric material layer with a height-dependent lateral etch distance that increases with a vertical distance from a top surface of the substrate.   
     
     
         14 . The method of  claim 13 , further comprising forming a sacrificial fill material portion within the in-process first memory opening, wherein the sacrificial fill material portion protects sidewalls of the first insulating layers and the first spacer material layers during etching of the substantially vertical sidewall of the joint level dielectric material layer. 
     
     
         15 . The method of  claim 14 , further comprising:
 vertically recessing the sacrificial fill material portion to physically expose the substantially vertical sidewall of the joint level dielectric material layer;   anisotropically applying a patterning film over the joint level dielectric material layer and the sacrificial fill material portion; and   performing an aspect ratio-dependent anisotropic etch process that provides the height-dependent lateral etch distance that increases with the vertical distance from a top surface of the substrate.   
     
     
         16 . The method of  claim 15 , wherein the patterning film comprises a material selected from a photoresist material, amorphous carbon, and diamond-like carbon (DLC). 
     
     
         17 . The method of  claim 15 , further comprising:
 forming a sacrificial dielectric material layer over the joint level dielectric material layer, wherein the first memory opening is formed through the sacrificial dielectric material layer, the patterning film is formed on a top surface of the sacrificial dielectric material layer, and another tapered sidewall is formed on the sacrificial dielectric material layer during formation of the tapered sidewall of the joint level dielectric material layer; and   removing the sacrificial dielectric material layer selective to the joint level dielectric material layer after formation of the first memory opening.   
     
     
         18 . The method of  claim 14 , further comprising etching a material of the joint level dielectric material layer employing an etch process that provides a higher interfacial etch rate for the material of the joint level dielectric material layer at an interface between the joint level dielectric material layer and the sacrificial fill material portion than a bulk etch rate for the material of the joint level dielectric material layer. 
     
     
         19 . The method of  claim 18 , further comprising:
 removing protruding portion of the sacrificial fill material portion after formation of the tapered sidewall of the joint level dielectric material layer; and   forming a retro-tapered sacrificial cap within a volume laterally bounded by the tapered sidewall of the joint level dielectric material layer and vertically bounded by a horizontal plane including a top surface of the joint level dielectric material layer.   
     
     
         20 . The method of  claim 12 , wherein:
 the memory film comprises a lower portion located adjacent to the first alternating stack, an upper portion located adjacent to the second alternating stack, and a joint portion located between the lower portion and the upper portion and adjacent to the joint level dielectric material layer;   the tapered outer sidewall of the memory film is located in the joint portion of the memory film and contacts a tapered sidewall of the joint level dielectric material layer in the memory opening;   an outer sidewall of the lower portion and an outer sidewall of the upper portion of the memory film are either untapered or have a smaller taper angle than a taper angle of the tapered outer sidewall of the joint portion of the memory film;   the tapered outer sidewall of the joint portion of the memory film has a uniform taper angle throughout, and the uniform taper angle is in a range from 5 degrees to 45 degrees with respect to a vertical direction that is perpendicular to a top surface of the substrate;   an annular horizontal surface of the memory film contacts a horizontal bottom surface of the second alternating stack; and   an upper periphery of the tapered outer sidewall of the memory film adjoins an outer periphery of the annular horizontal surface of the memory film.