Flash memory

Abstract

A flash memory refreshes at a time before a read error might occur. A controller performs a first read operation and a second read operation using a sense amplifier. In the second read operation, a bit line potential controller draws out a potential of a bit line feeding the sense amplifier so that, if memory cell degradation has occurred, the degradation can be detected. For example, when first data read by the first read operation and second data read by the second read operation are determined to be different, the memory cell is refreshed.

What is claimed is: 
     
         1 . A flash memory, comprising:
 a plurality of memory cells;   a sense amplifier to read data stored in a pair of memory cells, wherein the pair of memory cells includes a first memory cell and a second memory cell;   a bit line potential controller configured to control a potential of a selected bit line; and   a controller,   wherein a data value is stored in the pair of memory cells, by storing the data value in the first memory cell and storing an inverted data value, corresponding to the inverse of the data value, in the second memory cell,   wherein the sense amplifier is coupled, at an input terminal, to a first bit line coupled to the first memory cell and to a second bit line coupled to the second memory cell, and the sense amplifier is configured to read the data value stored in the pair of memory cells, based on a first potential of the first bit line and a second potential of the second bit line,   wherein the controller is configured to perform:   a first read operation in which the first memory cell is made to draw out the first potential of the first bit line, the second memory cell is made to draw out the second potential of the second bit line, and concurrently, the sense amplifier is made to generate a first data read value,   a second read operation in which, based on the first data read value, a memory cell with a low threshold voltage of the pair of memory cells is made to draw out a third potential of a bit line coupled to the memory cell with the low threshold voltage, a memory cell with a high threshold voltage of the pair of memory cells and the bit line potential controller are made to draw out a fourth potential of a bit line coupled to the memory cell with a high threshold voltage, and concurrently, the sense amplifier is made to generate a second data read value based on the third potential and the fourth potential,   a first data comparison operation in which the first data read value and the second data read value are compared with each other, and   a first refresh operation in which, when the first data read value and the second data read value are determined to be different from each other in the first data comparison operation, the data value and the inverted data value stored in the pair of memory cells are rewritten in the pair of memory cells.   
     
     
         2 . The flash memory according to  claim 1 ,
 wherein, after performing the first refresh operation, the controller is further configured to perform the first read operation again, the second read operation again, and the first data comparison operation again, to the memory cell as a read target.   
     
     
         3 . The flash memory according to  claim 1 , wherein a first threshold voltage of the first memory cell depends on a first state and a second threshold voltage of the second memory cell depends on a second state. 
     
     
         4 . The flash memory according to  claim 3 , wherein, when the first data value is a logical “1”:
 the first threshold voltage is a low voltage, the first state is an erase state, the second threshold voltage is a high voltage, the second state is a write state, and the selected bit line is the second bit line. 
 
     
     
         5 . The flash memory according to  claim 4 , wherein:
 the bit line potential controller is configured to cause the second data read value to not match the first data read value when the first memory cell is degraded, and   the bit line potential controller is configured to cause the second data read value to match the first data read value when the first memory cell is not degraded.   
     
     
         6 . The flash memory of  claim 5 , wherein a nitride layer of the first memory cell is degraded by repeated electron injection and hole injection. 
     
     
         7 . The flash memory according to  claim 3 , wherein, when the first data value is a logical “0”:
 the first threshold voltage is a high voltage, the first state is a write state, the second threshold voltage is a low voltage, and the second state is an erase state, and the selected bit line is the first bit line. 
 
     
     
         8 . The flash memory according to  claim 7 , wherein:
 the bit line potential controller is configured to cause the second data read value to not match the first data read value when the second memory cell is degraded, and   the bit line potential controller is configured to cause the second data read value to match the first data read value when the second memory cell is not degraded.   
     
     
         9 . The flash memory according to  claim 1 , further comprising a latch, wherein the latch is configured to store the first data read value after the first read operation and before the second read operation. 
     
     
         10 . The flash memory according to  claim 9 , wherein the bit line potential controller is further configured to:
 control the potential of the selected bit line by providing a reference current with respect to the selected bit line, and   apply the reference current to the selected bit line based on an input from the latch.   
     
     
         11 . A flash memory, comprising:
 a plurality of memory cells;   a sense amplifier to read data stored in a pair of memory cells, wherein the pair of memory cells includes a first memory cell and a second memory cell;   a bit line potential controller configured to control a potential of a selected bit line;   an error corrector configured to generate error correcting data, and to correct a first error output by the sense amplifier; and   a controller,   wherein a data value is stored in the pair of memory cells, by storing the data value in the first memory cell and storing an inverted data value, corresponding to the inverse of the data value, in the second memory cell,   wherein the sense amplifier is coupled, at an input terminal, to a first bit line coupled to the first memory cell and to a second bit line coupled to the second memory cell, and the sense amplifier is configured to read the data value stored in the pair of memory cells, based on a first potential of the first bit line and a second potential of the second bit line,   wherein the controller is configured to perform:   a first read operation in which the first memory cell is made to draw out the first potential of the first bit line, the second memory cell is made to draw out the second potential of the second bit line, and concurrently, the sense amplifier is made to generate a first data read value,   a second read operation in which, based on the first data read value, a memory cell with a low threshold voltage of the pair of memory cells is made to draw out a third potential of a bit line coupled to the memory cell with the low threshold voltage, a memory cell with a high threshold voltage of the pair of memory cells and the bit line potential controller are made to draw out a fourth potential of a bit line coupled to the memory cell with a high threshold voltage, and concurrently, the sense amplifier is made to generate a second data read value based on the third potential and the fourth potential,   a first error detection operation in which the error corrector is made to detect an error of the first data read value based on the second data read value and based on error correcting data,   a first refresh operation in which, when the error corrector detects an error of the second data read value, the error corrector is made to generate error corrected data of which the error is corrected based on the second data read value and the error correcting data, and   write the error corrected data in the pair of memory cells.   
     
     
         12 . The flash memory according to  claim 11 ,
 wherein, after performing the first refresh operation, the controller is further configured to perform the first read operation again, the second read operation again, and the first error detection operation again, to the memory cell as a target.   
     
     
         13 . The flash memory according to  claim 11 , wherein a first threshold voltage of the first memory cell depends on a first state and a second threshold voltage of the second memory cell depends on a second state. 
     
     
         14 . The flash memory according to  claim 13 , wherein, when the first data value is a logical “1”:
 the first threshold voltage is a low voltage, the first state is an erase state, the second threshold voltage is a high voltage, the second state is a write state, and the selected bit line is the second bit line. 
 
     
     
         15 . The flash memory according to  claim 14 , wherein:
 the bit line potential controller is configured to cause the second data read value to not match the first data read value when the first memory cell is degraded, and   the bit line potential controller is configured to cause the second data read value to match the first data read value when the first memory cell is not degraded.   
     
     
         16 . The flash memory of  claim 15 , wherein a nitride layer of the first memory cell is degraded by repeated electron injection and hole injection. 
     
     
         17 . The flash memory according to  claim 13 , wherein, when the first data value is a logical “0”:
 the first threshold voltage is a high voltage, the first state is a write state, the second threshold voltage is a low voltage, and the second state is an erase state, and the selected bit line is the first bit line. 
 
     
     
         18 . The flash memory according to  claim 17 , wherein:
 the bit line potential controller is configured to cause the second data read value to not match the first data read value when the second memory cell is degraded, and   the bit line potential controller is configured to cause the second data read value to match the first data read value when the second memory cell is not degraded.   
     
     
         19 . The flash memory according to  claim 11 , further comprising a latch, wherein the latch is configured to store the first data read value after the first read operation and before the second read operation. 
     
     
         20 . The flash memory according to  claim 19 , wherein the bit line potential controller is further configured to:
 control the potential of the selected bit line by providing a reference current with respect to the selected bit line, and   apply the reference current to the selected bit line based on an input from the latch.