Simultaneous write, read, and command-address-control calibration of an interface within a circuit

Abstract

A calibration controller tests an electronic circuit to iteratively perform, concurrently, a write test with a write delay, a read test with a read delay, and a CAC test with a CAC delay on an electronic circuit over a range of a plurality of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until a read edge, a write edge, and a CAC edge are detected for each condition of the range of the plurality of types of conditions. The calibration controller identifies, from the read edge, the write edge, and the CAC edge detected for each condition of the range of the plurality of types of conditions, a calibrated delay value for each of the write delay, the read delay, and the CAC delay for the range plurality of types of conditions to adjust the signal delays for each of write data, read data, and CAC data signal to arrive for latching within a separate valid window of time.

1 . A method, comprising:
 iteratively performing, by a computer, concurrently, a write test with a write delay, a read test with a read delay, and a CAC test with a CAC delay on an electronic circuit over a range of a plurality of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until a read edge, a write edge, and a CAC edge are detected for each condition of the range of the plurality of types of conditions; and   identifying, by the computer, from the read edge, the write edge, and the CAC edge detected for each condition of the range of the plurality of types of conditions, a calibrated delay value for each of the write delay, the read delay, and the CAC delay for the range plurality of types of conditions to adjust the signal delays for each of write data, read data, and CAC data signal to arrive for latching within a separate valid window of time.   
     
     
         2 . The method according to  claim 1 , further comprising:
 testing the electronic circuit to identify an initial read check with the read delay, an initial write check with the write delay, and an initial command, address, control (CAC) check with the CAC delay indicated as passing.   
     
     
         3 . The method according to  claim 2 , further comprising:
 responsive to passing the initial read check, the initial write check, and the initial CAC check, iteratively performing the write test with the write delay of a write timing delay setting concurrently with the read test with the read delay of a read timing delay and the CAC test with the CAC delay of a CAC timing delay setting over the range of conditions on the electronic circuit while simultaneously adjusting the write delay, adjusting the read delay, and adjusting the CAC delay for each iteration until one or more of a horizontal edge of the read edge, a horizontal edge of the write edge, and a horizontal edge of the CAC edge are detected.   
     
     
         4 . The method according to  claim 2 , further comprising:
 responsive to passing the initial read check, the initial write check, and the initial CAC check, iteratively performing the write test with the write delay of a write voltage reference setting concurrently with the read test with the read delay of a read voltage reference and the CAC test with the CAC delay of a CAC voltage reference setting over the range of conditions on the electronic circuit while simultaneously adjusting the write delay, adjusting the read delay, and adjusting the CAC delay for each iteration until one or more of a vertical edge of the read edge, a vertical edge of the write edge, and a vertical edge of the CAC edge are detected.   
     
     
         5 . The method according to  claim 2 , further comprising:
 checking read check results of the separate initial read check against one or more read parameters specified for read timing within the electronic circuit, wherein the one or more read parameters specify whether the initial read check results pass or fail;   checking write check results of the separate initial write check against one or more write parameters specified for write timing within the electronic circuit, wherein the one or more write parameters specify whether the initial write check results pass or fail;   checking CAC check results of the separate initial CAC check against one or more CAC parameters specified for CAC timing within the electronic circuit, wherein the one or more CAC parameters specify whether the initial CAC check results pass or fail; and   checking combined results of the simultaneous write test, read test, and CAC test against the one or more write parameters, the one or more read parameters, and the one or more CAC parameters.   
     
     
         6 . The method according to  claim 2 , further comprising:
 updating and testing each of the read delay setting, the write delay setting, and the CAC delay setting individually and until settings that result in a passing calibration test are identified for the read delay setting, the write delay setting, the CAC delay setting, a read voltage reference, a write voltage reference, a CAC voltage reference, a driver impedance and a slew rate.   
     
     
         7 . The method according to  claim 1 , further comprising:
 adjusting each condition of a range of conditions comprising one or more of a voltage, a reference voltage, a slew rate, a driver impedance, a receiver impedance, a frequency, a timing parameter, and a temperature refresh rate while calibrating a first value set as the write delay, a second value set as the read delay, and a third value set as the CAC delay.   
     
     
         8 . The method according to  claim 1 , further comprising:
 adjusting the write delay for adjusting the writing timing on a write interface between a memory controller and a memory of the electronic circuit; a   adjusting the read delay for adjusting the read timing on a read interface between the memory controller and the memory of the electronic circuit; and   adjusting the CAC delay for adjusting the CAC timing on a CAC interface between the memory controller and the memory of the electronic circuit.   
     
     
         9 . The method according to  claim 1 , further comprising:
 responsive to a particular iteration of the concurrent read test, write test, and CAC test resulting in an overall failed test, accessing one or more of a command address (CA) parity error signal, a write data cyclic redundancy cycle (CRC) error signal, and a read data CRC error signal to determine which of one or more settings under test from among the read delay, the write delay and the CAC delay caused the overall failed test; and   applying the one or more of the CA parity error signal and the CRC error signal to determine the one or more of the read edge, the write edge, and the CAC edge are detected.   
     
     
         10 . The method according to  claim 9 , further comprising:
 identifying the CRC error signal in an alert signal comprising a write CRC error signal in order to detect that the write delay under the write test caused the overall failed test.   
     
     
         11 . The method according to  claim 9 , further comprising:
 identifying the CRC error signal in an alert signal comprising a read CRC error signal in order to detect that the read delay under the read test caused the overall failed test.   
     
     
         12 . The method according to  claim 9 , further comprising:
 identifying the CA parity error signal in an alert signal in order to detect that the CAC delay under the CAC test caused the overall failed test.   
     
     
         13 . The method according to  claim 1 , further comprising:
 responsive to detecting the combined results of the simultaneous write test, read test, and CAC test fail:
 returning the CAC delay setting to a safe setting that has previously passed testing for one or more CAC parameters; and 
 rereading updated combined results of the simultaneous write test, read test, and CAC test with the CAC delay set to the safe setting; 
   checking updated combined results of the simultaneous write test, read test, and CAC test against one or more write parameters, one or more read parameters, and one or more CAC parameters;   responsive to detecting the updated combined results of the simultaneous write test, read test, and CAC test pass, detecting the CAC edge; and   responsive to detecting the updated combined results of the simultaneous write test, read test, and CAC test fail, performing at least one test to identify whether the read delay setting or the write delay setting caused the updated combined results to fail.   
     
     
         14 . A computer system comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions, stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:
 program instructions to iteratively perform, concurrently, a write test with a write delay, a read test with a read delay, and a CAC test with a CAC delay on an electronic circuit over a range of a plurality of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until a read edge, a write edge, and a CAC edge are detected for each condition of the range of the plurality of types of conditions; and   program instructions to identify, from the read edge, the write edge, and the CAC edge detected for each condition of the range of the plurality of types of conditions, a calibrated delay value for each of the write delay, the read delay, and the CAC delay for the range plurality of types of conditions to adjust the signal delays for each of write data, read data, and CAC data signal to arrive for latching within a separate valid window of time.   
     
     
         15 . The computer system according to  claim 14 , the stored program instructions further comprising:
 program instructions to test an electronic circuit to identify an initial read check with the read delay, an initial write check with the write delay, and an initial command, address, control (CAC) check with the CAC delay indicated as passing.   
     
     
         16 . The computer system according to  claim 15 , the stored program instructions to test an electronic circuit to identify an initial read check with a read delay setting, an initial write check with a write delay setting, and an initial command, address, control (CAC) check with a CAC delay setting indicated as passing further comprising:
 program instructions to update and testing each of the read delay setting, the write delay setting, and the CAC delay setting individually and until settings that result in a passing calibration test are identified for the read delay setting, the write delay setting, the CAC delay setting, a read voltage reference, a write voltage reference, a CAC voltage reference, a driver impedance and a slew rate.   
     
     
         17 . The computer system according to  claim 14 , the stored program instructions further comprising:
 program instructions to, responsive to a particular iteration of the concurrent read test, write test, and CAC test resulting in an overall failed test, access one or more of a command address (CA) parity error signal, a write data cyclic redundancy cycle (CRC) error signal, and a read data CRC error signal to determine which of one or more settings under test from among the read delay, the write delay and the CAC delay caused the overall failed test; and   program instructions to apply the one or more of the CA parity error signal and the CRC error signal to determine the one or more of the read edge, the write edge, and the CAC edge are detected.   
     
     
         18 . A computer program product comprising one or more computer-readable storage devices and program instructions, stored on at least one of the one or more storage devices, the stored program instructions comprising:
 program instructions to iteratively perform, concurrently, a write test with a write delay, a read test with a read delay, and a CAC test with a CAC delay on an electronic circuit over a range of a plurality of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until a read edge, a write edge, and a CAC edge are detected for each condition of the range of the plurality of types of conditions; and   program instructions to identify, from the read edge, the write edge, and the CAC edge detected for each condition of the range of the plurality of types of conditions, a calibrated delay value for each of the write delay, the read delay, and the CAC delay for the range plurality of types of conditions to adjust the signal delays for each of write data, read data, and CAC data signal to arrive for latching within a separate valid window of time.   
     
     
         19 . The computer program product according to  claim 18 , the stored program instructions further comprising:
 program instructions to, responsive to a particular iteration of the concurrent read test, write test, and CAC test resulting in an overall failed test, access one or more of a command address (CA) parity error signal, a write data cyclic redundancy cycle (CRC) error signal, and a read data CRC error signal to determine which of one or more settings under test from among the read delay, the write delay and the CAC delay caused the overall failed test; and   program instructions to apply the one or more of the CA parity error signal and the CRC error signal to determine the one or more of the read edge, the write edge, and the CAC edge are detected.   
     
     
         20 . The computer program product according to  claim 18 , the stored program instructions further comprising:
 program instructions to, responsive to detecting the combined results of the simultaneous write test, read test, and CAC test fail:
 return the CAC delay setting to a safe setting that has previously passed testing for one or more CAC parameters; and 
 reread updated combined results of the simultaneous write test, read test, 
   and CAC test with the CAC delay set to the safe setting;   program instructions to check updated combined results of the simultaneous write test, read test, and CAC test against one or more write parameters, one or more read parameters, and one or more CAC parameters;   program instructions to, responsive to detecting the updated combined results of the simultaneous write test, read test, and CAC test pass, detect the CAC edge; and   program instructions to, responsive to detecting the updated combined results of the simultaneous write test, read test, and CAC test fail, perform at least one test to identify whether the read delay setting or the write delay setting caused the updated combined results to fail.