Method and storage array for procesing a write data request

Abstract

According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.

What is claimed is: 
     
         1 . A method for processing a write data request in a storage array comprising an input/output manager, a switching device, a first controller, and a first cache device, and wherein the input/output manager, the first controller and the first cache device are coupled to the switching device, and the switching device is coupled to a storage unit in the storage array; the method comprising:
 obtaining, by the first controller for a write data request from the input/output manager via the switching device, a first cache address in the first cache device for storing an incoming data block of the write data request;   sending, by the first controller, an identifier of the first cache device and the first cache address to the input/output manager, via the switching device; and   writing, by the input/output manager, the incoming data block of the write data request to the first cache address via the switching device according to the identifier of the first cache device and the first cache address;   calculating, by the cache device, an eigenvalue of the incoming data block;   sending, by the cache device, the eigenvalue of the incoming data block to the first controller via the switching device;   receiving, by the first controller, the eigenvalue of the incoming data block;   searching, by the first controller, an eigenvalue index set of previously processed data blocks for the eigenvalue of the incoming data block; wherein the eigenvalue index set comprises a plurality of eigenvalue indices each comprising an eigenvalue of a respective data block in the previously processed data blocks and a storage address of the respective data block in a respective target storage unit, each of the previously processed data blocks being unique among the previously processed data blocks;   when the eigenvalue of the incoming data block is not in the eigenvalue index set, storing, by the first controller, the incoming data block into a target storage unit;   creating, by the first controller, an eigenvalue index of the incoming data block in the eigenvalue index set of data blocks, wherein the eigenvalue index of the incoming data block comprises the eigenvalue of the incoming data block and the storage address of the incoming data block in the target storage unit.   
     
     
         2 . The method according to  claim 1 , wherein the write data request includes an address of the incoming data block; and the method further comprises:
 receiving, by the input/output manager, a response sent by the first cache device, indicating that the incoming data block is written successfully;   sending a notification to the first controller from the input/output manager via the switching device, that the incoming data block is written to the first cache address; and   establishing by the first controller, according to the notification, a correspondence among the address of the incoming data block, the identifier of the first cache device, and the first cache address.   
     
     
         3 . The method according to  claim 1 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device, and the method further comprises:
 obtaining, by the first controller for the write data request, a second cache address from the second cache device for storing the incoming data block;   sending, by the first controller, an identifier of the second cache device and the second cache address to the input/output manager, via the switching device; and   writing, by the input/output manager, the incoming data block to the second cache address via the switching device, according to the identifier of the second cache device and the second cache address.   
     
     
         4 . The method according to  claim 1 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device, the method further comprising:
 obtaining, by the first controller for the write data request, a second cache address from the second cache device for storing the incoming data block;   sending, by the first controller, a write data instruction to the first cache device via the switching device, wherein the write data instruction includes an identifier of the second cache device and the second cache address; and   writing, by the first cache device, according to the write data instruction, the incoming data block to the second cache address, via the switching device.   
     
     
         5 . The method according to  claim 1 , wherein the write data request includes an address of the incoming data block, wherein the address of the incoming data block comprises an identifier of a target logical unit (LU) in which the incoming data block is located, a logical block address of the incoming data block, and a length of the incoming data block; and the method further comprising:
 querying, by the input/output manager, according to the identifier of the target LU, a homing relationship between the target LU and the first controller that is stored in the input/output manager, and identifying that the first controller is a home controller of the target LU; and   sending, by the input/output manager, the write data request to the first controller via the switching device.   
     
     
         6 . The method according to  claim 5 , wherein the method further comprising:
 establishing, by the first controller, a correspondence between the address of the incoming data block and the eigenvalue of the incoming data block.   
     
     
         7 . A storage array, including an input/output manager, a switching device, a first controller, and a first cache device, wherein the input/output manager, the first controller, and the first cache device are coupled to the switching device; and the switching device is coupled to a storage unit in the storage array;
 the first controller is configured to obtain, a first cache address in the first cache device for storing an incoming data block of the write data request, for the write data request, and send an identifier of the first cache device and the first cache address to the input/output manager via the switching device; and   the input/output manager is configured to write the incoming data block to the first cache address via the switching device according to the identifier of the first cache device and the first cache address;   the cache device is configured to calculate an eigenvalue of the incoming data block and send the eigenvalue of the incoming data block to the first controller via the switching device;   the first controller is further configured to receive the eigenvalue of the incoming data block, search an eigenvalue index set of previously processed data blocks for the eigenvalue of the incoming data block; wherein the eigenvalue index set comprises a plurality of eigenvalue indices each comprising an eigenvalue of a respective data block in the previously processed data blocks and a storage address of the respective data block in a respective target storage unit, each of the previously processed data blocks being unique among the previously processed data blocks, store the incoming data block into a target storage unit when the eigenvalue of the incoming data block is not in the eigenvalue index set, and create an eigenvalue index of the incoming data block in the eigenvalue index set of data blocks, wherein the eigenvalue index of the incoming data block comprises the eigenvalue of the incoming data block and the storage address of the incoming data block in the target storage unit.   
     
     
         8 . The storage array according to  claim 7 , wherein the write data request includes an address of the incoming data block;
 the input/output manager is further configured to receive from the first cache device, a response indicating that the incoming data block is written successfully, and send a notification to the first controller, via the switching device, that the incoming data block is written to the first cache address; and   the first controller is further configured to establish a correspondence among the address of the incoming data block, the identifier of the first cache device, and the first cache address, according to the notification.   
     
     
         9 . The storage array according to  claim 7 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device;
 the first controller is further configured to obtain, for the write data request, a second cache address from the second cache device for storing the incoming data block, and send an identifier of the second cache device and the second cache address to the input/output manager via the switching device; and   the input/output manager is further configured to write the incoming data block to the second cache address via the switching device, according to the identifier of the second cache device and the second cache address.   
     
     
         10 . The storage array according to  claim 7 , wherein the first controller is further configured to obtain a second cache address from the second cache device for storing the incoming data block for the write data request, and send a write data instruction to the first cache device via the switching device, wherein the write data instruction includes an identifier of the second cache device and the second cache address; and
 the first cache device is further configured to write the incoming data block to the second cache address via the switching device, according to the write data instruction.   
     
     
         11 . The storage array according to  claim 7 , wherein the write data request includes an address of the incoming data block, wherein the address of the incoming data block comprises an identifier of a target logical unit (LU) in which the incoming data block is located, a logical block address of the incoming data block, and a length of the incoming data block; and the input/output manager is further configured to query a homing relationship between the target LU and the first controller that is stored in the input/output manager according to the identifier of the target LU, identify that the first controller is a home controller of the target LU, and send the write data request to the first controller via the switching device. 
     
     
         12 . The storage array according to  claim 7 , wherein the first controller is further configured to establish a correspondence between the address of the incoming data block and the eigenvalue of the incoming data block.