On-chip sequence profiler

Abstract

A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.

1 . A method for profiling on-chip application sequences comprising:
 generating, for a profiling event to track a first bit sequence as it is applied to the internal latches of a chip and to determine whether the first bit sequence was executed successfully, a matrix for a finite state machine, the matrix comprising a field programmable gate array having programmable entries of expected values and having a first dimension corresponding to a sequence of time periods in the profiling event and having a second dimension corresponding to a set of profilers, wherein a programmable element of the matrix stores a control signal applied to a first profiler during a first time period of the sequence of time periods, and wherein the profiling event is a first profiling event of a set of profiling events and the programmable element of the matrix is programmed for each profiling event in the set of profiling events;   storing, in a first latch of the first profiler, a first bit of a scan sequence;   selecting, by a first multiplexer of the first profiler based on the first bit, the first bit sequence of a set of two or more bit sequences;   determining, by a second multiplexer of the first profiler based on the control signal, whether to capture the first bit sequence;   latching, by a second latch of the first profiler in response to determining to capture the first bit sequence, a second bit of the first bit sequence during the first time period;   determining, by the finite state machine, whether the latched second bit has an expected value, the expected value indicated by the control signal and the first time period;   disabling, in response to determining that the second bit has the expected value, the second latch; and   disabling, in response to determining that the second bit does not have the expected value, the profiling event.