US2018315762A1PendingUtilityA1

Semiconductor devices

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Apr 27, 2017Filed: Dec 14, 2017Published: Nov 1, 2018
Est. expiryApr 27, 2037(~10.7 yrs left)· nominal 20-yr term from priority
H10W 20/435H10W 20/42H10W 20/40H10W 20/069H10W 20/0698H01L 27/1104H01L 23/5226H01L 29/785H01L 23/5283H10D 84/0149H10D 84/0135H10D 84/0158H10D 30/62H10D 84/834H10D 84/038H10D 64/512H10B 10/12H10B 10/18
48
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Claims

Abstract

Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction;   a first gate structure that extends across the first active pattern and the second active pattern;   a second gate structure that is spaced apart from the first gate structure; and   a node contact between the first gate structure and the second gate structure that electrically connects the first active pattern and the second active pattern to each other,   wherein the node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern,   the second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first end of the node contact is spaced apart from the first gate structure at a first distance,
 the second end of the node contact being spaced apart from the first gate structure at a second distance greater than the first distance.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the second end of the node contact is spaced apart from the second gate structure at a third distance less than the first and second distances. 
     
     
         4 . The semiconductor device of  claim 2 , further comprising a third gate structure that is spaced apart from the first gate structure across the node contact and extends across the first active pattern,
 wherein the first end of the node contact is spaced apart from the third gate structure at about the first distance.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the node contact has a bent line shape extending in the second direction in a plan view of the semiconductor device. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a gate contact on the second gate structure,
 wherein the gate contact is connected to the node contact.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the second gate structure is electrically connected to the first active pattern and the second active pattern through the gate contact and the node contact. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the gate contact comprises a same material as that of the node contact. 
     
     
         9 . The semiconductor device of  claim 6 , wherein the contact has a top surface at a same height as that of a top surface of the node contact relative to the substrate. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the first active pattern and the second active pattern have different conductivity types from each other. 
     
     
         11 . The semiconductor device, comprising:
 a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction;   a first gate structure that extends across the first and second active patterns; and   a node contact on a side of the first gate structure that electrically connects the first active pattern and the second active pattern to each other,   wherein the node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern,   the first end of the node contact being spaced apart from the first gate structure, at a first distance, and the second end of the node contact being spaced apart from the first gate structure at a second distance greater than the first distance.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the node contact has a bent line shape, the node contact and the first gate structure extending in the second direction in a plan view of the semiconductor device. 
     
     
         13 . The semiconductor device of  claim 11 , further comprising a second gate structure that is spaced apart from the first gate structure across the node contact and partially overlaps the second active pattern,
 wherein the second end of the node contact is positioned closer to the second gate, structure than to the first gate structure.   
     
     
         14 . The semiconductor device of  claim 13 , further comprising a third gate structure that is spaced apart from the first gate structure across the node contact and extends across the first active pattern,
 wherein a pitch between the first and second gate structures is the same as a pitch between the first and third gate structures.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the first end of the node contact is spaced apart from the third gate structure at about the first distance. 
     
     
         16 . A semiconductor device, comprising:
 a first gate structure on a substrate;   a second gate structure spaced apart in a first direction from the first gate structure; and   a third gate structure spaced apart in the first direction fro, the first gate structure;   a node contact between the first gate structure and the second gate structure and between the first gate structure and the third gate structure;   wherein the second gate structure and the third gate structure are aligned with each other in a second direction crossing the first direction, and   wherein the node contact comprises a first end between the first structure and the third gate structure and a second end between the first gate structure and the second gate structure,   the second end of the node contact being shifted, in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.   
     
     
         17 . The semiconductor device of  claim 16 , wherein at least a portion of the node contact extends in parallel to the first gate structure and the third gate structure. 
     
     
         18 . The semiconductor device of  claim 16 , wherein
 the second gate structure comprises a gate electrode on the substrate and a gate spacer on a sidewall, of the gate electrode, and   the second end of the node contact is spaced apart from the gate electrode across the gate spacer.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising a gate contact connected to the gate electrode of the second gate structure,
 wherein the gate contact is connected to the node contact, and   wherein the gate electrode of the second gate structure is electrically connected to the substrate through the gate contact and the node contact.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the gate contact. and the node contact have respective top surfaces at a same height relative to the substrate.

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