Hetero-integration of iii-n material on silicon

Abstract

A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.

1 . A method for forming a hetero-integrated device, comprising:
 etching a trench in a monocrystalline Si substrate through an opening in a dielectric layer to expose a continuous crystal surface at a bottom of the trench;   forming remnants of a protection layer on the continuous crystal surface; and   growing at least one III-V material layer from the continuous crystal surface at the bottom of the trench, the at least one III-V material layer being electrically isolated from the sidewalls of the trench.   
     
     
         2 . The method as recited in  claim 1 , wherein forming the remnants of the protection layer further comprises:
 depositing the protection layer on the continuous crystal surface; and   removing the protection layer from the continuous crystal surface at the bottom of the trench such that reactants from the protection layer protect the continuous crystal surface.   
     
     
         3 . The method as recited in  claim 1 , wherein the protection layer is formed from AN. 
     
     
         4 . The method as recited in  claim 1 , further comprising depositing sidewall dielectric spacers on sidewalls of the trench, with the sidewall dielectric spacers including a nitride or oxide material. 
     
     
         5 . The method as recited in  claim 4 , wherein the sidewall dielectric spacers are formed to have a thickness of between about 30 nm and 100 nm. 
     
     
         6 . The method as recited in  claim 1 , wherein etching the trench includes exposing a (111) crystal surface at the bottom of the trench. 
     
     
         7 . The method as recited in  claim 1 , wherein etching the trench in the substrate includes etching the trench in a silicon layer of a silicon-on-insulator (SOI) substrate. 
     
     
         8 . The method as recited in  claim 1 , wherein growing the at least one III-V material layer includes forming at least one of a transistor, a diode or a laser. 
     
     
         9 . The method as recited in  claim 1 , wherein the at least one III-V material layer includes GaN. 
     
     
         10 . The method as recited in  claim 1 , further comprising forming a source contact, a drain contact, and a gate metal on the at least one III-V material layer. 
     
     
         11 . The method as recited in  claim 1 , further comprising forming a multiple quantum well (MQW) structure on the at least one III-V material layer. 
     
     
         12 . A method for forming a hetero-integrated device, comprising:
 etching a trench in a monocrystalline Si substrate through an opening in a dielectric layer to expose a continuous (111) crystal surface at a bottom of the trench;   forming remnants of an AlN layer on the continuous crystal surface; and   growing at least one III-V material layer from the continuous (111) crystal surface at the bottom of the trench, the at least one III-V material layer being electrically isolated from the sidewalls of the trench.   
     
     
         13 . The method as recited in  claim 12 , wherein forming the remnants of the AlN layer further comprises:
 depositing the AlN layer on the continuous (111) crystal surface; and   removing the AlN layer from the continuous (111) crystal surface at the bottom of the trench such that reactants from the AlN layer protect the continuous (111) crystal surface.   
     
     
         14 . The method as recited in  claim 12 , further comprising depositing sidewall dielectric spacers on sidewalls of the trench, with the sidewall dielectric spacers including a nitride or oxide material. 
     
     
         15 . The method as recited in  claim 14 , wherein the sidewall dielectric spacers are formed to have a thickness of between about 30 nm and 100 nm. 
     
     
         16 . The method as recited in  claim 12 , wherein etching the trench in the substrate includes etching the trench in a silicon layer of a silicon-on-insulator (SOI) substrate. 
     
     
         17 . The method as recited in  claim 12 , wherein growing the at least one III-V material layer includes forming at least one of a transistor, a diode or a laser. 
     
     
         18 . The method as recited in  claim 12 , wherein the at least one III-V material layer includes GaN. 
     
     
         19 . The method as recited in  claim 12 , further comprising forming a source contact, a drain contact, and a gate metal on the at least one III-V material layer. 
     
     
         20 . The method as recited in  claim 12 , further comprising forming a multiple quantum well (MQW) structure on the at least one III-V material layer.