Peripheral component

Abstract

Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

What is claimed is: 
     
         1 . A system comprising:
 a first bus;   a CPU in communication with the first bus;   a first component having a first bridge in communication with the CPU via the first bus and in communication with a second bus; and   a second component in communication with the first component via the second bus and in communication with the CPU via the first bus, through the second bus.   
     
     
         2 . The system of  claim 1  wherein:
 communication between the first bus and the first component includes a bidirectional transfer of data between the first bus and the first component; and 
 communication between the first component and the second component includes a bidirectional transfer of data between the first component and the second component via the second bus. 
 
     
     
         3 . The system of  claim 1  wherein the first and second components are first and second graphics processing units (GPUs). 
     
     
         4 . The system of  claim 2 , wherein:
 communication between the second component and the CPU further includes a unidirectional transfer of data from the second component to the CPU via a third bus.   
     
     
         5 . The system of  claim 4 , wherein:
 communication from the CPU to the second component occurs through the first component but not through the third bus; and   communication from the second component to the CPU occurs through the third bus but not through the first component.   
     
     
         6 . The system of  claim 3 , wherein:
 communication between the second component and the CPU occurs via the first component and does not occur directly.   
     
     
         7 . The system of  claim 6 , wherein the second component does not include a bridge. 
     
     
         8 . The system of  claim 1 , wherein the first bridge comprises a peripheral component interconnect express bridge (“PCIe bridge”). 
     
     
         9 . A method comprising:
 communicating between a CPU and a first bus;   communicating, via a first bus, with a first bridge of a first component; and   communicating, via the first bus, the first bridge, and a second bus coupled between the first component and a second component, between the second component and the CPU.   
     
     
         10 . The method of  claim 9 , wherein:
 communication between the first bus and the first component includes a bidirectional transfer of data between the first bus and the first component; and   communication between the first component and the second component includes a bidirectional transfer of data between the first component and the second component via the second bus.   
     
     
         11 . The method of  claim 10 , wherein:
 communication from the CPU to the second component occurs through the first component but not through the third bus; and   communication from the second component to the CPU occurs through the third bus but not through the first component.   
     
     
         12 . The method of  claim 11 , wherein:
 communication between the second component and the CPU occurs via the first component and does not occur directly.   
     
     
         13 . The method of  claim 12 , wherein the second component does not include a bridge. 
     
     
         14 . The method of  claim 9 , wherein the first bridge comprises a peripheral component interconnect express bridge (“PCIe bridge”).