Level-shifting circuits and related methods and apparatus

Abstract

Techniques and devices for level-shifting a signal are described. A level-shifting circuit may include an input terminal and components. The input terminal may be configured to receive a logical signal compatible with a first power domain. The components may be configured to convert the logical signal to a second power domain and to provide the converted logical signal at an output terminal. The components may include a resistive device coupled between the output terminal and the input terminal, and/or a capacitive device coupled between the resistive device and the input terminal.

1 - 12 . (canceled) 
     
     
         13 . A level-shifter circuit comprising:
 first and second inverters, wherein an output terminal of the first inverter is coupled to an input terminal of the second inverter;   a resistive device coupled between an input terminal of the first inverter and an output terminal of the second inverter; and   a first capacitive device coupled between the input terminal of the first inverter and an input terminal of the level-shifter circuit.   
     
     
         14 . The level-shifter circuit of  claim 13 , further comprising:
 a second capacitive device coupled between the input terminal of the first inverter and a voltage supply at a first potential; and   a third capacitive device coupled between the input terminal of the first inverter and a voltage supply at a second potential.   
     
     
         15 . The level-shifter circuit of  claim 13 , wherein at least one FET of the first inverter is implemented in core logic, and wherein at least one FET of the second inverter is implemented in core logic. 
     
     
         16 . The level-shifter circuit of  claim 13 , wherein a propagation delay between the input and output terminals of the level-shifter circuit is between 5 picoseconds and 100 picoseconds. 
     
     
         17 . The level-shifter circuit of  claim 13 , wherein a capacitance of the first capacitive device is between 3 times and 30 times a parasitic capacitance at the input terminal of the first inverter. 
     
     
         18 . The level-shifter circuit of  claim 13 , further comprising first and second differential output terminals, wherein the first differential output terminal is coupled to the output terminal of the second inverter. 
     
     
         19 . The level-shifter circuit of  claim 18 , wherein the second differential output terminal is coupled to the output terminal of the first inverter. 
     
     
         20 . (canceled) 
     
     
         21 . The level-shifter circuit of  claim 13 , wherein a first level-shifting unit comprises the first and second inverters, the resistive device, and the first capacitive device, wherein the level-shifter circuit further comprises a second level-shifting unit, and wherein an input terminal of the second level-shifting circuit is coupled to the output terminal of the first level-shifting circuit. 
     
     
         22 . The level-shifter circuit of  claim 21 , wherein the second level-shifting unit comprises a multi-stage level-shifting unit. 
     
     
         23 . The level-shifter circuit of  claim 13 , further comprising reset circuitry configured to set the potential of a node between the first capacitive device and the resistive device in response to a reset control signal. 
     
     
         24 . A level-shifter circuit comprising:
 an input terminal configured to receive a first logical signal compatible with a first power domain; and   a plurality of components configured to convert the first logical signal to a second logical signal compatible with a second power domain different from the first power domain and to provide the second logical signal at an output terminal,   wherein the plurality of components includes a resistive device configured to conductively couple the output terminal and the input terminal, one or more of the components being configured to conduct a current between the input terminal and the output terminal via the resistive device based on a change in a voltage of the first logical signal.   
     
     
         25 . The level-shifter circuit of  claim 24 , wherein the plurality of components further includes a capacitive device coupled between the resistive device and the input terminal. 
     
     
         26 . The level-shifter circuit of  claim 24 , wherein a propagation delay between the input and output terminals of the level-shifter circuit is between 5 picoseconds and 100 picoseconds. 
     
     
         27 . The level-shifter circuit of  claim 24 , wherein the plurality of components further includes a differential pair of field-effect transistors (FETs) of a first type coupled to a cross-coupled pair of FETs of a second type. 
     
     
         28 . A power train device comprising:
 a level-shifter circuit including:   first and second inverters, wherein an output terminal of the first inverter is coupled to an input terminal of the second inverter;   a resistive device coupled between an input terminal of the first inverter and an output terminal of the second inverter; and   a first capacitive device coupled between the input terminal of the first inverter and an input terminal of the level-shifter circuit.