Embedded sige process for multi-threshold pmos transistors

Abstract

An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first PMOS transistor with source and drain extensions and with pockets, the first PMOS transistor having SiGe source and drains with a first SiGe cavity to gate distance;   a second PMOS transistor without source and drain extensions and without pockets, the second PMOS transistor having SiGe source and drains with a second SiGe cavity to gate distance; and   wherein the second SiGe cavity to gate distance is smaller than the first SiGe cavity to gate distance and wherein a turn on voltage of the second PMOS transistor is lower than the turn on voltage of the first PMOS transistor.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the turn on voltage of the second PMOS transistor is at least 50 mV lower than the turn on voltage of the first PMOS transistor. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the turn on voltage of the second PMOS transistor is about 200 mV lower than the turn on voltage of the first PMOS transistor. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the first SiGe cavity to gate distance is approximately three times the second SiGe cavity to gate distance. 
     
     
         5 . The integrated circuit of  claim 1 , further comprising SiGe spacer sidewalls on a gate of the first PMOS transistor and on a gate of the second PMOS transistor, wherein the SiGe spacer sidewalls are approximately 20 nm and wherein the first SiGe cavity to gate distance is approximately 15 nm and wherein the second SiGe cavity to gate distance is approximately 5 nm. 
     
     
         6 . An integrated circuit, comprising:
 a first PMOS transistor with source and drain extensions and with pockets, the first PMOS transistor having SiGe source and drains spaced a first distance from a gate of the first PMOS transistor;   a second PMOS transistor without source and drain extensions and without pockets, the second PMOS transistor having SiGe source and drains spaced a second distance from a gate of the second PMOS transistor; and   wherein the second distance is smaller than the first distance and wherein a turn on voltage of the second PMOS transistor is lower than the turn on voltage of the first PMOS transistor.   
     
     
         7 . The integrated circuit of  claim 6 , wherein the turn on voltage of the second PMOS transistor is at least 50 mV lower than the turn on voltage of the first PMOS transistor. 
     
     
         8 . The integrated circuit of  claim 6 , wherein the turn on voltage of the second PMOS transistor is about 200 mV lower than the turn on voltage of the first PMOS transistor. 
     
     
         9 . The integrated circuit of  claim 6 , wherein the first distance is approximately three times the second distance. 
     
     
         10 . The integrated circuit of  claim 6 , further comprising SiGe spacer sidewalls on the gate of the first PMOS transistor and on the gate of the second PMOS transistor, wherein the SiGe spacer sidewalls are approximately 20 nm and wherein the first distance is approximately 15 nm and wherein the second distance is approximately 5 nm.