Radio-frequency switches having silicon-on-insulator field-effect transistors with reduced linear region resistance

Abstract

Disclosed are devices and methods related to radio-frequency (RF) switches having silicon-on-insulator (SOI) field-effect transistors (FETs). In some embodiments, an RF switch can include an FET with shaped source, drain, and gate selected to yield a reduced per-area value of resistance in linear operating region (Rds-on). In some implementations, a plurality of such FETs can be connected in series to allow use of SOI technology in high power RF switching applications while maintaining a relatively small die size.

1 . (canceled) 
     
     
         2 . A method for fabricating a transistor, the method comprising:
 forming or providing a silicon-on-insulator structure having an isolated well on an insulator layer;   forming one or more source regions and one or more drain regions in the well, the one or more source regions including a first shape, the one or more drain regions including a second shape, the first shape having a first facing portion and the second shape having a second facing portion, the first and second facing portions generally facing each other, one or both of the first and second facing portions having a plurality of segments that extend in different directions;   forming a gate between the one or more source regions and the one or more drain regions;   forming one or more electrical conductors that interconnect each of the one or more source regions; and   forming one or more electrical conductors that interconnect each of the one or more drain regions.   
     
     
         3 . The method of  claims 2  wherein the silicon-on-insulator structure includes a first insulator layer located above a substrate, and a well defined above the insulator layer. 
     
     
         4 . The method of  claim 3 , wherein the well is isolated by a second insulator layer disposed above the first insulator layer, the second insulator layer surrounding the well. 
     
     
         5 . The method of  claim 2  wherein the first and second facing portions define opposing sides of a quadrilateral other than a rectangle. 
     
     
         6 . The method of  claim 2  wherein the gate is disposed on the well and between the one or more source regions and the one or more drain regions. 
     
     
         7 . The method of  claim 2  wherein the said plurality of segments define a double-diamond shape. 
     
     
         8 . The method of  claim 2  wherein forming the one or more electrical conductors that interconnect each of the one or more source regions includes forming the one or more electrical conductors to extend in a zigzag along a first direction. 
     
     
         9 . The method of  claim 2  wherein forming the one or more electrical conductors that interconnect each of the one or more drain regions includes forming the one or more electrical conductors to extend in a zigzag along a first direction. 
     
     
         10 . The method of  claim 2  wherein forming the gate includes forming a single structure gate layer between the one or more source regions and the one or more drain regions. 
     
     
         11 . The method of  claim 2  wherein forming the one or more source regions and the one or more drain regions includes forming the one or more source regions to have a different orientation than the one or more drain regions. 
     
     
         12 . The method of  claim 11  wherein the one or more source regions is oriented at approximately ninety degrees to the one or more drain regions. 
     
     
         13 . The method of  claim 2  wherein forming the one or more source regions and forming the one or more drain regions includes forming a plurality of source and drain regions arranged in a two-dimensional array including a plurality of rows and a plurality of columns. 
     
     
         14 . A method for fabricating a radio-frequency switching device, the method comprising:
 forming or providing a silicon-on-insulator structure having an isolated well on an insulator layer;   forming a plurality of source regions and a plurality of drain regions in the well, each of the source regions including a first shape having a first facing portion, each of the drain regions including a second shape having a second facing portion, the first and second facing portions substantially facing each other, one or both of the first and second facing portions having a plurality of segments that extend in different directions;   forming a gate between the source regions and the drain regions;   forming one or more electrical conductors that interconnect each of the source regions; and   forming one or more electrical conductors that interconnect each of the drain regions.   
     
     
         15 . The method of  claims 14  wherein the silicon-on-insulator structure includes a first insulator layer located above a substrate, a well defined above the insulator layer, and a second insulator layer disposed above the first insulator layer, the second insulator layer surrounding the well. 
     
     
         16 . The method of  claim 14  wherein the first and second facing portions define opposing sides of a quadrilateral other than a rectangle. 
     
     
         17 . The method of  claim 14  wherein the gate is disposed on the well and between the source regions and the drain regions. 
     
     
         18 . The method of  claim 14  wherein the said plurality of segments define a double-diamond shape. 
     
     
         19 . The method of  claim 14  wherein forming the gate includes forming a single structure gate layer between the source regions and the drain regions. 
     
     
         20 . The method of  claim 14  wherein forming the source regions and the drain regions includes forming the source regions to have a different orientation than the drain regions. 
     
     
         21 . The method of  claim 20  wherein the source regions are oriented at approximately ninety degrees to the drain regions.