Adding cap to copper passivation flow for electroless plating

Abstract

An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 an interconnect region;   a top interconnect level disposed in said interconnect region;   a metal element of said top interconnect level;   a metal seed layer disposed over said metal element and making electrical connection to said metal element;   a copper pad of electroplated copper disposed over said seed layer, said copper pad making electrical connection to said seed layer;   a metal cap layer of plated metal free of copper disposed on a top surface of said copper pad;   an upper protective overcoat disposed over said integrated circuit, said upper protective overcoat overlapping a top surface of said metal cap layer and covering said lateral surface of said copper pad, said upper protective overcoat having a bond pad opening which exposes said top surface of said metal cap layer; and   a bond pad of electroless plated metal disposed in said bond pad opening, said bond pad making electrical connection to said metal cap layer.   
     
     
         2 . The integrated circuit of  claim 1 , in which said metal cap layer includes nickel between 1 to 3 microns thick; 
     
     
         3 . The integrated circuit of  claim 1 , in which said metal cap layer includes a metal selected from the group consisting of: nickel, palladium, gold and any combination thereof. 
     
     
         4 . The integrated circuit of  claim 1 , in which said metal cap layer includes electroplated metal. 
     
     
         5 . The integrated circuit of  claim 1 , in which said metal cap layer includes electroless plated metal. 
     
     
         6 . The integrated circuit of  claim 1 , in which said upper protective overcoat includes polyimide. 
     
     
         7 . The integrated circuit of  claim 1 , in which said seed layer includes:
 a sputtered layer of titanium tungsten alloy contacting said metal element; and   a sputtered layer of copper on said layer of titanium tungsten alloy.   
     
     
         8 . The integrated circuit of  claim 1 , in which said bond pad provides a wirebond pad. 
     
     
         9 . The integrated circuit of  claim 1 , in which a top surface of said bond pad is coplanar with a top surface of said upper protective overcoat within 100 nanometers. 
     
     
         10 . The integrated circuit of  claim 1 , further including a second metal element of said top interconnect level, said seed layer making electrical connection to said second metal element and said seed layer and said copper pad extending continuously from said first metal element to said second metal element. 
     
     
         11 . An integrated circuit, comprising:
 a top interconnect level;   a metal element of said top interconnect level;   a metal seed layer disposed over said metal element and making electrical connection to said metal element;   a copper pad disposed over said seed layer, said copper pad making electrical connection to said seed layer;   a non-copper metal cap layer disposed on a top surface of said copper pad;   a protective overcoat disposed over said integrated circuit, said protective overcoat overlapping a top surface of said non-copper metal cap layer and covering said lateral surface of said copper pad, said protective overcoat having a bond pad opening which exposes said top surface of said non-copper metal cap layer; and   a bond pad of metal disposed in said bond pad opening, said bond pad making electrical connection to said non-copper metal cap layer.   
     
     
         12 . The integrated circuit of  claim 11 , in which said metal cap layer includes nickel between 1 to 3 microns thick; 
     
     
         13 . The integrated circuit of  claim 11 , in which said metal cap layer includes a metal selected from the group consisting of: nickel, palladium, gold and any combination thereof. 
     
     
         14 . The integrated circuit of  claim 11 , in which said seed layer includes a layer of titanium tungsten alloy contacting said metal element. 
     
     
         15 . The integrated circuit of  claim 11 , further including a second metal element of said top interconnect level, said seed layer making electrical connection to said second metal element and said seed layer and said copper pad extending continuously from said first metal element to said second metal element.