Package structure and manufacturing method thereof

Abstract

A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.

What is claimed is: 
     
         1 . A package structure comprising:
 a first redistribution structure having a first surface and a second surface opposite to the first surface;   a chip, disposed on the first surface of the first redistribution structure and having an active surface and a rear surface opposite to the active surface;   an insulation encapsulation, encapsulating the chip and the first surface of the first redistribution structure; and   a protection layer, directly disposed on the rear surface of the chip.   
     
     
         2 . The package structure according to  claim 1 , wherein the first redistribution structure comprises at least one dielectric layer and a plurality of first conductive elements disposed in the at least one dielectric layer, and the chip is electrically connected to the first conductive elements exposed on the first surface. 
     
     
         3 . The package structure according to  claim 2 , further comprising a plurality of bumps, disposed between the active surface and the first surface of the first redistribution structure and electrically connected to the first conductive elements respectively. 
     
     
         4 . The package structure according to  claim 3 , wherein the surfaces of the bumps facing the first surface are substantially coplanar with a surface of the insulation encapsulation. 
     
     
         5 . The package structure according to  claim 1 , further comprising a second redistribution structure, disposed above the rear surface of the chip, the protection layer, and the insulation encapsulation. 
     
     
         6 . The package structure according to  claim 5 , further comprising a plurality of conductive pillars, surrounding the chip and disposed between the first redistribution structure and the second redistribution structure. 
     
     
         7 . The package structure according to  claim 6 , wherein the second redistribution structure comprises at least one dielectric layer and a plurality of second conductive elements disposed in the at least one dielectric layer, and the chip is electrically connected to the second conductive elements through the first redistribution structure and the conductive pillars. 
     
     
         8 . The package structure according to  claim 1 , further comprising an underfill, disposed between the first surface of the first redistribution structure and the active surface of the chip. 
     
     
         9 . The package structure according to  claim 1 , wherein a thickness of the protection layer ranges between 5 μm and 30 μm. 
     
     
         10 . The package structure according to  claim 1 , wherein the chip is electrically connected to the first redistribution structure through a flip-chip bonding process. 
     
     
         11 . A manufacturing method of a package structure, comprising:
 providing a first carrier substrate;   forming a first redistribution structure having a first surface and a second surface opposite to the first surface on the first carrier substrate, wherein the first surface is attached to the first carrier substrate;   providing a second carrier substrate attached to the second surface of the first redistribution structure;   separating the first redistribution structure from the first carrier substrate; and   disposing a chip on the first surface of the first redistribution structure, wherein the chip has an active surface and a rear surface opposite to the active surface, a protection layer is directly formed on the rear surface, and the active surface of the chip is adhered to the first surface of the first redistribution structure.   
     
     
         12 . The method according to  claim 11 , further comprising forming a first release layer between the first carrier substrate and the first redistribution structure. 
     
     
         13 . The method according to  claim 11 , further comprising forming a second release layer between the second carrier substrate and the second surface of the first redistribution structure for separating the second carrier substrate from the first redistribution structure. 
     
     
         14 . The method according to  claim 11 , wherein the step of forming the first redistribution structure further comprises forming at least one dielectric layer and a plurality of first conductive elements, and the chip is electrically connected to the first conductive elements. 
     
     
         15 . The method according to  claim 14 , further comprising forming a plurality of conductive pillars on the first surface of the first redistribution structure, wherein the conductive pillars surround the chip. 
     
     
         16 . The method according to  claim 15 , further comprising encapsulating the chip, the protection layer, and the conductive pillars by utilizing an insulation encapsulation. 
     
     
         17 . The method according to  claim 16 , wherein the step of encapsulating the chip, the protection layer and the conductive pillars comprises:
 disposing the insulation encapsulation over the chip, the protection layer, and the conductive pillars; and   reducing a thickness of the insulation encapsulation to expose top surfaces of the conductive pillars.   
     
     
         18 . The method according to  claim 17 , further comprising forming a second redistribution structure above the insulation encapsulation. 
     
     
         19 . The method according to  claim 18 , wherein the step of forming the second redistribution structure comprises forming at least one dielectric layer and a plurality of second conductive elements, and the conductive pillars are electrically connected between the first conductive elements and the second conductive elements respectively. 
     
     
         20 . The method according to  claim 11 , wherein the step of disposing the chip on the first surface of the first redistribution structure comprises forming a plurality of bumps between the active surface of the chip and the first surface of the first redistribution structure.