Semiconductor Device with Metallization Structure and Method for Manufacturing Thereof

Abstract

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate comprising a first side and a second side;   at least one doping region formed at the first side of the semiconductor substrate;   a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region; and   a second metallization structure at the second side of the semiconductor substrate, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor substrate comprises SiC. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the semiconductor substrate comprises:
 a first doping region of a first conductivity type at the first side of the semiconductor substrate;   a second doping region of a second conductivity type at the first side of the semiconductor substrate,   wherein the first metallization structure is on and in contact with the first doping region of the first conductivity type and the second doping region of the second conductivity type.   
     
     
         4 . The semiconductor device of  claim 1 , wherein the at least one silicide interface region and the at least one non-silicide interface region of the second metallization structure are in contact with an additional doping region formed at the second side of the semiconductor substrate. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second metallization structure comprises first metallization regions and second metallization regions, wherein the first metallization regions form the respective silicide interface regions with the semiconductor substrate, and wherein the second metallization regions form the respective non-silicide interface regions with the semiconductor substrate. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the second metallization regions surround the first metallization regions and/or the second metallization regions are in direct contact with the semiconductor substrate. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the first metallization regions and the second metallization regions comprise different metals. 
     
     
         8 . The semiconductor device of  claim 5 , wherein the first metallization regions comprise at least one of nickel, nickel alloy containing nickel as main component, titanium, titanium alloy containing titanium as main component, a metal nitride, a metal silicide, platinum, and aluminium, or a combination thereof, and wherein the silicide interface regions comprise a metal silicide. 
     
     
         9 . The semiconductor device of  claim 5 , wherein the second metallization structure comprises a second metal layer comprising the second metallization regions, and wherein the second metal layer completely covers the first metallization regions. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the second metal layer and the second metallization regions comprise at least one of titanium, titanium alloy containing titanium as main component, a metal nitride such as titanium nitride, platinum, and aluminum, or a combination thereof. 
     
     
         11 . The semiconductor device of  claim 5 , further comprising:
 n-type doped regions at the second side of the semiconductor substrate between the first metallization regions.   
     
     
         12 . The semiconductor device of  claim 1 , further comprising:
 a passivation structure at the first side of the semiconductor substrate,   wherein the passivation structure covers lateral edges of the first metallization structure and comprises at least one opening to expose a central part of the first metallization structure.   
     
     
         13 . The semiconductor device of  claim 1 , wherein the semiconductor device is one of a bipolar device power device and a unipolar power device. 
     
     
         14 . The semiconductor device of  claim 1 , further comprising:
 a carrier substrate comprising a lead structure,   wherein the semiconductor device is soldered with the second metallization structure to the lead structure of the carrier substrate.   
     
     
         15 . A method for manufacturing a semiconductor device, the method comprising:
 providing a semiconductor substrate comprising a first side and a second side;   forming at least one doping region at the first side of the semiconductor substrate;   forming a first metallization structure at the first side of the semiconductor substrate on and in contact with the at least one doping region; and   subsequently forming a second metallization structure at the second side of the semiconductor substrate, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.   
     
     
         16 . The method of  claim 15 , wherein forming the second metallization structure comprises:
 forming first metallization regions on and in contact with the second side of the semiconductor substrate;   thermally annealing the first metallization regions to form the at least one or respective silicide interface regions between the first metallization regions and the semiconductor substrate; and   forming second metallization regions on and in contact with the second side of the semiconductor substrate, the second metallization regions forming the at least one or respective non-silicide interface regions with the semiconductor substrate.   
     
     
         17 . The method of  claim 16 ,
 wherein forming the first metallization regions comprises forming a first metal layer on and in contact with the second side of the semiconductor substrate, and etching the first metal layer using an etching mask to form the first metallization regions; and   wherein forming second metallization regions comprises forming a second metal layer which completely covers the first metallization regions and which forms, between the first metallization regions, the second metallization regions.   
     
     
         18 . The method of  claim 15 , further comprising:
 forming, prior to forming the second metallization structure, a passivation structure at the first side of the semiconductor substrate, the passivation structure covering lateral edges of the first metallization structure and comprises at least one opening to expose a central part of the first metallization structure.   
     
     
         19 . A method for manufacturing a semiconductor device, the method comprising:
 providing a semiconductor substrate comprising a first side and a second side;   forming a first metal layer on and in contact with the second side of the semiconductor substrate;   forming a mask on the first metal layer, the mask comprising openings exposing portions of the first metal layer;   etching the first metal layer using the mask as an etching mask to remove the exposed portions of the first metal layer from the second side of the semiconductor substrate and to form first metallization regions which remain on the second side of the semiconductor substrate;   heating the first metallization regions and the second side of the semiconductor substrate to form silicide interface regions between the first metallization regions and the semiconductor substrate, the second side of the semiconductor substrate being heated to a higher temperature than the first side of the semiconductor substrate; and   forming a second metal layer on and in contact with the second side of the semiconductor substrate, the second metal layer completely covering the first metallization regions and forming one or more non-silicide interface regions with the semiconductor substrate.   
     
     
         20 . The method of  claim 19 , further comprising, prior to forming the first metal layer:
 forming at least one doping region at the first side of the semiconductor substrate;   forming a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region; and   
     
     
         21 . The method of  claim 19 , further comprising:
 forming a passivation structure at the first side of the semiconductor substrate, the passivation structure covering lateral edges of the first metallization structure and comprising at least one opening to expose a central part of the first metallization structure.   
     
     
         22 . The method of  claim 19 , wherein heating the first metallization regions and the second side of the semiconductor substrate comprises:
 directing at least one laser beam on the first metallization regions and the second side of the semiconductor substrate.   
     
     
         23 . The method of  claim 19 , further comprising:
 implanting n-type dopants into the second side of the semiconductor substrate after formation of the first metallization regions.