Clock management block

Abstract

A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a configurable circuit configured to receive at least first and second control signals respectively associated with first and second clock domain via switching circuitry in the configurable circuit and configured to receive at least one clock signal; and   clock management circuitry configured to generate the first and second control signals, wherein the switching circuitry is configured to route at least one of the first and second control signals to at least one output of the switching circuitry.   
     
     
         2 . The integrated circuit defined in  claim 1 , wherein the clock management circuitry comprises first and second clock management circuits configured to respectively generate the first and second control signals at least based in part on respective first and second input clock signals. 
     
     
         3 . The integrated circuit defined in  claim 2 , wherein the first input clock signal is the clock signal received by the configurable circuit. 
     
     
         4 . The integrated circuit defined in  claim 2 , wherein the first and second clock management circuits are communicatively coupled with each other. 
     
     
         5 . The integrated circuit defined in  claim 2 , wherein the first clock management circuit comprises logic circuitry and a control signal distribution network interposed between the logic circuitry and the configurable circuit. 
     
     
         6 . The integrated circuit defined in  claim 5 , wherein the logic circuitry is coupled to an additional configurable circuit that configures the first clock management circuit. 
     
     
         7 . The integrated circuit defined in  claim 1 , wherein the first and second controls signals comprise first and second initialization control signals, and wherein the configurable circuit comprises a storage circuit coupled to the output of the switching circuitry. 
     
     
         8 . The integrated circuit defined in  claim 1 , wherein the configurable circuit comprises a reconfiguration signal generator configured to generate a reconfigurable signal based at least in part on the one of the first and second control signals. 
     
     
         9 . The integrated circuit defined in  claim 1 , wherein the configurable circuit is configured to receive third and fourth control signals respectively associated with the first and second clock domain via the switching circuitry and wherein the switching circuitry is configured to route at least one of the third and fourth control signals to an additional output of the switching circuitry. 
     
     
         10 . An integrated circuit, comprising:
 programmable circuitry configured to selectively operate in at least one of a first clock domain and a second clock domain;   a first clock management block configured to provide a first signal associated with the first clock domain to the programmable circuitry; and   a second clock management block configured to provide a second signal associated with the second clock domain to the programmable circuitry, wherein the first and second clock management blocks are coupled to each other.   
     
     
         11 . The integrated circuit defined in  claim 10 , wherein a first portion of the programmable circuitry is configured to receive the first signal and operate in the first clock domain and wherein a second portion of the programmable circuitry is configured to receive the second signal and operate in the second clock domain. 
     
     
         12 . The integrated circuit defined in  claim 11 , wherein the first portion of the programmable circuitry is a first fabric tile and the second portion of the programmable circuitry is a second fabric tile. 
     
     
         13 . The integrated circuit defined in  claim 10 , wherein the programmable circuitry comprises a reconfiguration signal generator configured to selectively reconfigure programmable logic based at least in part on the first signal. 
     
     
         14 . The integrated circuit defined in  claim 10 , wherein the programmable circuitry comprises a reconfiguration signal generator configured to selectively reconfigure programmable interconnects based at least in part on the second signal. 
     
     
         15 . An electronic device, comprising:
 configurable circuitry;   a clock generation circuit configured to receive a reference clock signal and generate at least one output clock signal based on the reference clock signal;   a clock management circuit configured to receive the output clock signal and generate at least a control signal associated with the output clock signal, wherein the configurable circuitry is configured to receive the control signal and the output clock signal; and   a sampling circuit configured to provide an align signal to the clock management circuit to align an operation of the configurable circuitry to the reference clock signal.   
     
     
         16 . The electronic device defined in  claim 15 , wherein the output clock signal comprises a sub-cycle clock signal based on the reference clock signal. 
     
     
         17 . The electronic device defined in  claim 15 , wherein the clock management circuit comprises counter circuitry and wherein the sampling circuit is configured to align an operation of the counter circuitry to the reference clock signal. 
     
     
         18 . The electronic device defined in  claim 15 , wherein the sample circuitry is configured to receive the reference clock signal and the control signal associated with the reference clock signal. 
     
     
         19 . The electronic device defined in  claim 15 , wherein the clock management circuit is coupled to additional configurable circuitry via a fabric interface. 
     
     
         20 . The electronic device defined in  claim 15 , wherein the clock generation circuit is configured to generate a plurality of output clock signals based on the reference clock signal and wherein switching circuit is configured to receive the plurality of the output clock signals and route one of the plurality of the output clock signals to the clock management circuit and configurable circuitry.