Semiconductor device and a manufacturing method thereof

Abstract

In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

What is claimed is: 
     
         1 . A method for manufacturing a semiconductor device, comprising the steps of:
 (a) providing a semiconductor substrate;   (b) forming a first insulation film including a charge accumulation part over the semiconductor substrate in a first region;   (c) forming a first gate electrode over the first insulation film in the first region;   (d) forming a second insulation film covering respective side surfaces on the opposite sides of the first gate electrode in the gate length direction of the first gate electrode;   (e) performing etching using the second insulation film as a mask, and thereby processing the first insulation film; and   (f) performing ion implantation using the second insulation film as a mask, and thereby forming first source/drain regions at the top surface of the semiconductor substrate in the first region,   wherein a first transistor including the first gate electrode and the first source/drain regions forms a nonvolatile storage element.   
     
     
         2 . The method for manufacturing a semiconductor device according to  claim 1 , further comprising the steps of:
 (b1) forming a third insulation film over the semiconductor substrate in a second region; and   (c1) forming a second gate electrode over the third insulation film in the second region,   wherein in the step (d), the second insulation film covering each of the side surfaces on the opposite sides of the first gate electrode in the gate length direction of the first gate electrode, and the side surfaces on the opposite sides of the second gate electrode in the gate length direction of the second gate electrode is formed,   the method further comprising the steps of:   (e1) performing etching using the second insulation film as a mask, and thereby processing the third insulation film; and   (f1) performing ion implantation using the second insulation film as a mask, and thereby forming second source/drain regions at the top surface of the semiconductor substrate in the second region,   wherein the second gate electrode and the second source/drain regions form a second transistor.   
     
     
         3 . The method for manufacturing a semiconductor device according to  claim 2 ,
 wherein the step (d) includes the steps of:   (d1) depositing the second insulation film covering each of the first gate electrode and the second gate electrode over the top surface of the semiconductor substrate; and   (d2) subjecting the second insulation film to anisotropic etching, and thereby exposing the top surface of the semiconductor substrate from the second insulation film.   
     
     
         4 . The method for manufacturing a semiconductor device according to  claim 2 ,
 wherein the second transistor is a selection transistor, and   wherein the first transistor and the second transistor form one memory cell, and are coupled in series with each other.   
     
     
         5 . The method for manufacturing a semiconductor device according to  claim 1 ,
 wherein in the gate length direction of the first gate electrode, the ends of the first insulation film protrude outwardly from the side surfaces of the first gate electrode, respectively.   
     
     
         6 . The method for manufacturing a semiconductor device according to  claim 2 ,
 wherein in the gate length direction of the first gate electrode, the ends of the first insulation film protrude outwardly from the side surfaces of the first gate electrode, respectively,   wherein in the gate length direction of the second gate electrode, the ends of the third insulation film protrude outwardly from the side surfaces of the second gate electrode, respectively, and   wherein a distance between the side surface of the first gate electrode in the gate length direction of the first gate electrode and a termination of the first insulation film is smaller than a distance between the side surface of the second gate electrode in the gate length direction of the second gate electrode and the termination of the third insulation film.   
     
     
         7 . The method for manufacturing a semiconductor device according to  claim 1 , further comprising the steps of:
 (a2) forming a semiconductor layer over the semiconductor substrate in a third region via a buried insulation film;   (b2) forming a fourth insulation film over the semiconductor layer; and   (c2) forming a third gate electrode over the fourth insulation film in the third region,   wherein in the step (d), the second insulation film covering each of the side surfaces on the opposite sides of the first gate electrode in the gate length direction of the first gate electrode, and the side surfaces on the opposite sides of the third gate electrode in the gate length direction of the third gate electrode is formed,   the method further comprising the steps of:   (e2) performing etching using the second insulation film as a mask, and thereby processing the fourth insulation film; and   (f2) performing ion implantation using the second insulation film as a mask, and thereby forming third source/drain regions at the top surface of the semiconductor layer in the third region,   wherein the third gate electrode and the third source/drain regions form a second transistor.   
     
     
         8 . The method for manufacturing a semiconductor device according to  claim 7 ,
 wherein the step (d) includes the steps of:   (d3) sequentially stacking a fifth insulation film and a sixth insulation film over the top surface of the semiconductor substrate in the first region and the third region in such a manner as to cover each of the first gate electrode and the third gate electrode, and thereby forming the second insulation film including the fifth insulation film and the sixth insulation film; and   (d4) subjecting the sixth insulation film to anisotropic etching, and thereby exposing the top surface of the fifth insulation film,   wherein the step (f) includes the steps of:   (f4) after the step (e), with the third region covered with a protective film, forming a pair of first semiconductor regions having a first conductivity type at the top surface of the semiconductor substrate in the first region, and then, removing the protective film; and   (f5) forming a pair of second semiconductor regions having the first conductivity type, and having a higher density than that of the first semiconductor region at the top surface of the semiconductor substrate in the first region, and thereby forming the first source/drain regions each formed of the first semiconductor region and the second semiconductor region,   the method further comprising the steps of:   (g) after the step (f4), forming a seventh insulation film covering the side surface of the third gate electrode via the second insulation film;   (h) removing the fifth insulation film and the fourth insulation film exposed from the seventh insulation film, and then, forming an epitaxial layer over the top surface of the semiconductor layer; and   (i) before the step (f5), removing the seventh insulation film, and a part of the fifth insulation film, and thereby exposing each of the top surface of the semiconductor layer, and the top surface of the semiconductor substrate in the first region from the fifth insulation film.   
     
     
         9 . The method for manufacturing a semiconductor device according to  claim 8 ,
 wherein the step (f4) includes the steps of:   (f6) after the step (e), with the third region covered with the protective film, causing the top surface of the first insulation film in the first region to be retreated to an intermediate depth of the first insulation film; and   (f7) after the step (f6), with the third region covered with the protective film, forming a pair of first semiconductor regions having a first conductivity type at the top surface of the semiconductor substrate in the first region, and then, removing the protective film.   
     
     
         10 . The method for manufacturing a semiconductor device according to  claim 2 ,
 wherein the charge accumulation part is formed of an eighth insulation film having a higher dielectric constant than that of silicon nitride, and   wherein the step (b), the step (b1), the step (c1), and the step (c) are sequentially performed.   
     
     
         11 . A semiconductor device having:
 a semiconductor substrate;   a first gate electrode formed over the semiconductor substrate in a first region via a first insulation film including a charge accumulation film;   a first offset spacer formed of a second insulation film covering the side surface of the first gate electrode;   first source/drain regions formed at the top surface of the semiconductor substrate in the first region;   a second gate electrode formed over the semiconductor substrate in a second region via a third insulation film;   a second offset spacer formed of a fourth insulation film covering the side surface of the second gate electrode; and   second source/drain regions formed at the top surface of the semiconductor substrate in the second region,   wherein a first transistor including the first gate electrode and the first source/drain regions forms a nonvolatile storage element,   wherein a second transistor including the second gate electrode and the second source/drain regions forms a selection transistor,   wherein the first transistor and the second transistor form one memory cell, and are coupled in series with each other,   wherein in the gate length direction of the first gate electrode, the ends of the first insulation film protrude outwardly from the side surfaces of the first gate electrode, respectively, and   wherein in the gate length direction of the second gate electrode, the ends of the third insulation film protrude outwardly from the side surfaces of the second gate electrode, respectively.   
     
     
         12 . The semiconductor device according to  claim 11 , further comprising:
 a first sidewall covering the side surface of the first gate electrode via the first offset spacer;   a second sidewall covering the side surface of the second gate electrode via the second offset spacer; and   a dented part formed at the top surface of the semiconductor substrate immediately under the second sidewall,   wherein the position of the bottom surface of the dented part is lower than the position of the top surface of the semiconductor substrate immediately under the first sidewall, and   wherein the film thickness of the third insulation film is smaller than the film thickness of the first insulation film.   
     
     
         13 . A semiconductor device, comprising:
 a semiconductor substrate;   a semiconductor layer formed over the semiconductor substrate in each of a first region and a second region via a buried oxide film;   a first gate electrode formed over the semiconductor layer in the first region via a first insulation film including a charge accumulation film;   a first offset spacer formed of a second insulation film covering the side surface of the first gate electrode;   first source/drain regions formed at the top surface of the semiconductor layer in the first region;   a second gate electrode formed over the semiconductor layer in the second region via a third insulation film;   a second offset spacer formed of a fourth insulation film covering the side surface of the second gate electrode; and   second source/drain regions formed at the top surface of the semiconductor layer in the second region,   wherein a first transistor including the first gate electrode, and the first source/drain regions forms a nonvolatile storage element,   wherein a second transistor including the second gate electrode, and the second source/drain regions forms a selection transistor,   wherein the first transistor and the second transistor form one memory cell, and are coupled in series with each other,   wherein in the gate length direction of the first gate electrode, the ends of the first insulation film protrude outwardly from the side surfaces of the first gate electrode, respectively, and   wherein in the gate length direction of the second gate electrode, the ends of the third insulation film protrude outwardly from the side surfaces of the second gate electrode, respectively.   
     
     
         14 . The semiconductor device according to  claim 13 , further comprising:
 a first sidewall covering the side surface of the first gate electrode via the first offset spacer;   a second sidewall covering the side surface of the second gate electrode via the second offset spacer; and   a dented part formed at the top surface of the semiconductor layer immediately under the second sidewall,   wherein the position of the bottom surface of the dented part is lower than the position of the top surface of the semiconductor layer immediately under the first sidewall, and   wherein the film thickness of the third insulation film is smaller than the film thickness of the first insulation film.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein the difference between the film thickness of the third insulation film and the film thickness of the first insulation film is smaller than the film thickness of the semiconductor layer.