Semiconductor memory device and method of forming the same

Abstract

A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a plurality of active areas, defined on a semiconductor substrate;   a shallow trench isolation, disposed in the semiconductor substrate, wherein the active areas are surrounded by the shallow trench isolation;   a plurality of trenches, disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches comprises a bottom surface and a saddle portion protruded therefrom in each active areas; and   a plurality of gates, disposed in the trenches respectively.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein a length of the saddle portion in a projection direction is smaller than a length of the active area in the projection direction. 
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein the semiconductor memory device further comprises:
 a plurality of bit lines, disposed on the semiconductor substrate and across the active areas and the gates.   
     
     
         4 . The semiconductor memory device according to  claim 3 , wherein portions of the bit lines where crossing the active areas are close to the bottom surface. 
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein the gates comprise:
 a dielectric layer, covered on a surface of the trenches;   a conductive layer; and   a capping layer filling the trenches.   
     
     
         6 . The semiconductor memory device according to  claim 1 , wherein the bottom surface of the trenches located in the active areas is flush with a bottom surface of the trenches located in the shallow trench isolation. 
     
     
         7 . A method of fabricating a semiconductor memory device, comprising:
 forming a shallow trench isolation in a semiconductor substrate to define a plurality of active areas;   forming a plurality of trenches in the semiconductor substrate, penetrated through the active areas and the shallow trench isolation, wherein each of the trenches comprises a arc-shaped bottom surface in each active areas; and   performing an etching process to remove the arc-shaped bottom surface, thereby forming a planar bottom surface and a saddle portion protruding upward in the active areas.   
     
     
         8 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein the method further comprises:
 performing a oxidation of the arc-shaped bottom surface before the etching process is performed.   
     
     
         9 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein the etching process comprises a soft-etching process. 
     
     
         10 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein the formation of the trenches comprises:
 performing a removal process of the shallow trench isolation; and   performing a removal process of the semiconductor substrate to form the trenches.   
     
     
         11 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein the method further comprises:
 forming a plurality of gates, disposed in the trenches respectively; and   forming a plurality of bit lines, disposed on the semiconductor substrate, wherein the bit lines cross the active areas and the gates.   
     
     
         12 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein a length of the saddle portion in a projection direction is smaller than a length of the active area in the projection direction. 
     
     
         13 . The method of fabricating a semiconductor memory device according to  claim 7 , wherein a curvature of the saddle portion is greater than a curvature of the arc-shaped bottom surface.