Processing Techniques for Silicon-Based Transient Devices

Abstract

Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate. The components may independently comprise a selectively transformable material and, optionally, further have a preselected transience profile. The components are transfer printed, thereby decoupling the component fabrication step from additional processing to provide desired device functionality and transient properties. A substrate layer is provided on top of the components and used to facilitate handling, processing, and/or device functionality.

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         2 . A method of making a transient electronic device comprising the steps of:
 fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate; wherein the one or more inorganic semiconductor components or one or more metallic conductor components independently comprise a selectively transformable material and have a preselected transience profile;   providing a patterned substrate comprising one or more components of an electronic device on a receiving surface of the patterned substrate;   transfer printing the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate to the receiving surface of the patterned substrate; and   integrating the one or more inorganic semiconductor components, one or more metallic components or one or more inorganic semiconductor components and one or more metallic conductor components with the one or more electronic device components on the receiving surface of the patterned substrate, thereby making said transient electronic device.   
     
     
         3 . The method of  claim 1 , wherein said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate is carried out at a semiconductor foundry. 
     
     
         4 . The method of  claim 2 , wherein said steps other than said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate are not carried out in a semiconductor foundry. 
     
     
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         24 . The method of  claim 2 , wherein the fabricating step comprises forming a plurality of semiconductor components on the mother substrate. 
     
     
         25 . The method of  claim 24 , wherein the fabricating step further comprises undercutting the semiconductor components. 
     
     
         26 . The method of  claim 25 , wherein the plurality of semiconductor components are freestanding on the mother substrate and connected to the mother substrate by one or more anchors. 
     
     
         27 . The method of  claim 2 , wherein the mother substrate comprises a silicon-on-insulator (SOI) wafer. 
     
     
         28 . The method of  claim 27 , wherein the SOI wafer has a <111> orientation. 
     
     
         29 . The method of  claim 27 , wherein the SOI wafer comprises:
 a silicon handle wafer having a <111> orientation;   a buried insulator layer; and   a top layer of active Si having a <100> orientation from which the one or more semiconductor components are formed.   
     
     
         30 . The method of  claim 29 , further comprising the step of: etching the Si <111> handle wafer to facilitate release of the one or more semiconductor device components that comprise Si <100> from the mother substrate. 
     
     
         31 . The method of  claim 29 , wherein the SOI wafer comprises a commercial quality SOI wafer that is coated with the buried insulator layer that is an oxide layer, and the oxide layer is bonded to a bulk <111>-oriented silicon wafer. 
     
     
         32 . The method of  claim 31 , wherein the oxide layer comprises silicon dioxide. 
     
     
         33 . The method of  claim 2 , wherein the transfer printing comprises dry transfer contact printing. 
     
     
         34 . The method of  claim 33 , wherein the dry transfer printing further comprises contacting the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components with a transfer device;
 removing the transfer device and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate;   contacting the transfer device and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to the handle substrate; and   removing the transfer device without the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components, thereby transferring the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to the handle substrate.   
     
     
         35 . The method of  claim 33 , wherein the transfer device comprises an elastomeric stamp. 
     
     
         36 . The method of  claim 2 , wherein the transfer printing is high throughput and high fidelity. 
     
     
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         53 . The method of  claim 2 , wherein the transience profile is selected by adjusting any one or more of:
 a thickness of the semiconductor or the metallic conductor components;   a density of the semiconductor or the metallic conductor components;   a defect density of the semiconductor or the metallic conductor components;   a composition of the semiconductor or the metallic conductor components;   a porosity of the semiconductor or the metallic conductor components;   a crystallinity of the semiconductor or the metallic conductor components;   a dopant of the semiconductor or the metallic conductor components; or   a morphology of the semiconductor or the metallic conductor components.   
     
     
         54 . The method of  claim 2 , wherein the one or more metallic conductor components are independently selected from the group consisting of Mg, Mo, W, Fe, Zn and alloys thereof. 
     
     
         55 . The method of  claim 2  comprising fabricating a plurality of inorganic semiconductor components. 
     
     
         56 . The method of  claim 55 , wherein the processing step comprises providing one or more metallic components. 
     
     
         57 . The method of  claim 2 , wherein the one or more metallic components comprise interconnects that electrically interconnect one or more semiconductor components. 
     
     
         58 . The method of  claim 2 , wherein the metallic components comprise electrodes in electrical communication with the one or more semiconductor components. 
     
     
         59 . The method of  claim 2 , wherein the metallic components are provided by a deposition technique. 
     
     
         60 . The method of  claim 59 , wherein the deposition technique is selected from the group consisting of physical vapor deposition, chemical vapor deposition, sputtering, epitaxial growth, atomic layer deposition, electrochemical deposition, electrohydrodynamic jet printing, and molecular beam epitaxy. 
     
     
         61 . The method of  claim 2 , wherein the one or more inorganic semiconductor components or one or more metallic conductor components is microsized, having a lateral dimension that is greater than or equal to 5 μm and less than or equal to 500 μm. 
     
     
         62 . The method of  claim 2 , wherein the transient electronic device comprises a metal-oxide semiconductor field-effect transistor (MOSFET); a complementary metal-oxide-semiconductor (CMOS), a transistor, a capacitive sensor, a diode, a photodector, or a capacitor. 
     
     
         63 . The method of  claim 2 , wherein the transient electronic device is a communication system, a photonic device, a sensor, an optoelectronic device, a biomedical device, a temperature sensor, a photodetector, a photovoltaic device, a strain gauge, an imaging system, a wireless transmitter, an antenna, a battery, a nanoelectromechanical system or a microelectromechanical system. 
     
     
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         65 . The method of  claim 2 , wherein the one or more inorganic semiconductor components or the one or more metallic conductor components independently comprise one or more thin film structures. 
     
     
         66 . The method of  claim 65 , wherein the one or more thin film structures each independently have a thickness selected over a range that is greater than or equal to 10 nm and less than or equal to 100 μm. 
     
     
         67 . The method of  claim 2 , wherein the transient electronic device degrades in response to an environmental signal. 
     
     
         68 . The method of  claim 2 , wherein the transient electronic device degrades in response to a user-initiated signal. 
     
     
         69 . The method of  claim 2 , wherein the selectively transformable material has an electrical dissolution rate selected from the range of 0.01 nm/day to 100 μm/s. 
     
     
         70 . The method of  claim 2 , wherein the preselected transience profile is characterized by one or more of:
 a transformation of 0.01% to 100% of said one or more inorganic semiconductor components or said one or more metallic conductor components over a time interval selected from the range of 1 ms to 5 years;   a decrease in average thickness of said one or more inorganic semiconductor components or said one or more metallic conductor components at a rate selected over the range of 0.01 nm/day to 100 microns s −1 ;   a decrease in electrical conductivity of said one or more inorganic semiconductor components or said one or more metallic conductor components at a rate selected over the range of 10 10 S□m −1 s −1  to 1 S□m −1  s −1 ;   a change in morphology of said one or more inorganic semiconductor components or said one or more metallic conductor components, said change in morphology selected from the group consisting of pitting, flaking, cracking and uniform degradation;   a percentage decrease in density of said one or more inorganic semiconductor components or said one or more metallic conductor components selected over the range of 0.01% to 99.9%; or   a percentage increase in porosity of said one or more inorganic semiconductor components or said one or more metallic conductor components selected over the range of 0.01% to 99.9%.