Removal of trilayer resist without damage to underlying structure

Abstract

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region. The middle layer is disposed between the top layer and a bottom layer of the trilayer photoresist structure. The middle layer and the bottom layer in the first region are removed to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region. The first region is filled to protect the at least one first structure. The middle layer in the second region is removed while the at least one first structure remains protected.

What is claimed is: 
     
         1 . A method for semiconductor processing, comprising:
 removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region, the middle layer being disposed between the top layer and a bottom layer of the trilayer photoresist structure;   removing the middle layer and the bottom layer in the first region to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region;   filling the first region to protect the at least one first structure; and   removing the middle layer in the second region while the at least one first structure remains protected.   
     
     
         2 . The method as recited in  claim 1 , wherein the trilayer photoresist structure includes an organic layer, inorganic layer and organic layer, respectively, for the top layer, the middle layer and the bottom layer. 
     
     
         3 . The method as recited in  claim 1 , wherein the middle layer is resistant to etchants employed to etch the top layer and the bottom layer; 
     
     
         4 . The method as recited in  claim 1 , wherein filling the first region includes depositing a planarization layer. 
     
     
         5 . The method as recited in  claim 1 , wherein the bottom layer and the planarization layer include a same material. 
     
     
         6 . The method as recited in  claim 1 , wherein the bottom layer and the planarization layer include an organic planarization layer (OPL). 
     
     
         7 . The method as recited in  claim 1 , wherein the middle layer includes an anti-reflection coating. 
     
     
         8 . The method as recited in  claim 1 , further comprising exposing the at least one first structure and at least one second structure in the second region. 
     
     
         9 . A method for semiconductor processing, comprising:
 removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region, the middle layer being disposed between the top layer and a bottom layer of the trilayer photoresist structure;   removing the middle layer and the bottom layer in the first region to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region;   processing the at least one first structure;   forming a planarization layer over the middle layer in the second region and the at least one first structure;   removing the planarization layer in the second region, and removing the planarization layer in the first region down to a position located between the middle layer in the second region and the at least one first structure; and   removing the middle layer in the second region by performing a selective etch process while the at least one first structure remains protected by the planarization layer in the first region.   
     
     
         10 . The method as recited in  claim 9 , wherein the trilayer photoresist structure includes an organic layer, inorganic layer and organic layer, respectively, for the top layer, the middle layer and the bottom layer. 
     
     
         11 . The method as recited in  claim 9 , wherein the middle layer is resistant to etchants employed to etch the top layer and the bottom layer; 
     
     
         12 . The method as recited in  claim 9 , wherein processing the at least one first structure includes performing a spacer etch. 
     
     
         13 . The method as recited in  claim 9 , wherein the bottom layer and the planarization layer include a same material. 
     
     
         14 . The method as recited in  claim 9 , wherein the bottom layer and the planarization layer include an organic planarization layer (OPL), and the middle layer includes an anti-reflection coating. 
     
     
         15 . The method as recited in  claim 9 , further comprising exposing the at least one first structure and at least one second structure in the second region, including removing the planarization layer in the first region and the bottom layer in the second region. 
     
     
         16 . A method for semiconductor processing, comprising:
 removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region, the middle layer being disposed between the top layer and a bottom layer of the trilayer photoresist structure;   removing the middle layer and the bottom layer in the first region to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region;   processing the at least one first structure;   forming a planarization layer over the middle layer in the second region and the at least one first structure;   removing the planarization layer in the second region, and removing the planarization layer in the first region down to a position located between the middle layer in the second region and the at least one first structure; and   removing the middle layer in the second region by performing a polishing process while the at least one first structure remains protected by the planarization layer in the first region.   
     
     
         17 . The method as recited in  claim 17 , wherein the trilayer photoresist structure includes an organic layer, inorganic layer and organic layer, respectively, for the top layer, the middle layer and the bottom layer. 
     
     
         18 . The method as recited in  claim 17 , wherein the middle layer is resistant to etchants employed to etch the top layer and the bottom layer. 
     
     
         19 . The method as recited in  claim 17 , wherein the bottom layer and the planarization layer include an organic planarization layer (OPL), and wherein the middle layer includes an anti-reflection coating. 
     
     
         20 . The method as recited in  claim 17 , further comprising exposing the at least one first structure and at least one second structure in the second region, including removing the planarization layer in the first region and the bottom layer in the second region.