Signal receiver with multi-level sampling

Abstract

A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A system comprising:
 a plurality of parallel analog-to-digital converter (ADC) paths, wherein:
 each ADC path of the plurality of parallel ADC paths is assigned a different clock phase, 
 the different clock phases are time-interleaved and derived from a single clock, and 
 each of the plurality of parallel ADC paths comprises a track-and-hold followed by a sub-ADC. 
   
     
     
         22 . The system of  claim 21 , wherein:
 a first track-and-hold in a first ADC path is operated according to a first clock phase,   a second track-and-hold in a second ADC path is operated according to a second clock phase, and   a third track-and-hold in a third ADC path is operated according to a third clock phase.   
     
     
         23 . The system of  claim 21 , wherein the system is operable to generate the different clock phases. 
     
     
         24 . The system of  claim 23 , wherein:
 the plurality of parallel ADC paths comprises a first ADC path, a second ADC path and a third ADC path, and   an operation of the first ADC path, the second ADC path and the third ADC path is time-interleaved.   
     
     
         25 . The system of  claim 24 , wherein the interleaved operation of the ADC paths causes the ADC to:
 execute the sampling in the first ADC path during a first clock phase;   execute the sampling in the second ADC path during a second clock phase; and   execute the sampling in the third ADC path during a third clock phase.   
     
     
         26 . The system of  claim 23 , wherein the plurality of parallel ADC paths comprises a first ADC path, a second ADC path and a third ADC path. 
     
     
         27 . The system of  claim 21 , wherein the system comprises an amplifier operably coupled to an input of the plurality of parallel ADC paths. 
     
     
         28 . The system of  claim 21 , wherein the system comprises a second layer track-and-hold that is operable to generate the first signal by sampling a second signal. 
     
     
         29 . The system of  claim 28 , wherein the second layer track-and-hold uses the single clock. 
     
     
         30 . The system of  claim 28 , wherein the system comprises a first layer track-and-hold that is operable to generate the second signal by sampling a third signal. 
     
     
         31 . A method comprising:
 assigning a different clock phase to each path of a plurality of parallel analog-to-digital converter (ADC) paths, wherein the different clock phases are time-interleaved and derived from a single clock; and   performing in each of the plurality of parallel ADC paths:
 sampling a first signal, and 
 digitizing the sampled signal. 
   
     
     
         32 . The method of  claim 31 , comprising:
 generating a first clock phase, a second clock phase and a third clock phase; and   using the first clock phase, the second clock phase, and the third clock phase for sampling in a first path of the plurality of parallel ADC paths, a second path of the plurality of parallel ADC paths and a third path of the plurality of parallel ADC paths, respectively.   
     
     
         33 . The method of  claim 31 , wherein the method comprises generating the different clock phases. 
     
     
         34 . The method of  claim 33 , wherein:
 sampling a first signal comprises:
 a first periodic sampling in a first ADC path to generate a first sampled signal, 
 a second periodic sampling in a second ADC path to generate a second sampled signal, and 
 a third periodic sampling in a third ADC path to generate a third sampled signal, 
 wherein the first periodic sampling, the second periodic sampling, and the third periodic sampling are time-interleaved. 
   
     
     
         35 . The method of  claim 34 , wherein:
 the first periodic sampling occurs during a first clock phase,   the second periodic sampling occurs during a second clock phase, and   the third periodic sampling occurs during a third clock phase.   
     
     
         36 . The method of  claim 33 , wherein the plurality of parallel ADC paths comprises a first ADC path, a second ADC path and a third ADC path. 
     
     
         37 . The method of  claim 31 , wherein the method comprises amplifying the first signal. 
     
     
         38 . The method of  claim 31 , wherein the method comprises generating the first signal by sampling a second signal. 
     
     
         39 . The method of  claim 38 , wherein the second signal is sampled by the single clock. 
     
     
         40 . The method of  claim 38 , wherein the method comprises generating the second signal by sampling a third signal.