US2018277456A1PendingUtilityA1

Semiconductor device manufacturing method and semiconductor device

Assignee: RENESAS ELECTRONICS CORPPriority: Nov 10, 2005Filed: May 21, 2018Published: Sep 27, 2018
Est. expiryNov 10, 2025(expired)· nominal 20-yr term from priority
H10W 74/00H10W 90/284H10W 90/24H10W 72/5445H10W 90/754H10W 72/932H10W 72/59H10W 46/603H10W 46/301H10W 46/101H10W 90/00B23K 2103/56B23K 2103/50B23K 2101/40B23K 26/40G01R 31/2601B23K 26/53H10P 74/277H10P 72/7422H10P 72/7416H10P 74/273H10P 74/203H10P 72/7402H10P 72/0428H10P 72/78H10P 72/74H10P 54/00H10P 52/00H10P 34/42H10W 90/291H10W 72/983H10W 72/967H10W 46/503H10W 74/016H10W 70/093H10W 46/00H10W 42/121B23K 26/0006H01L 21/4853H01L 21/268B23K 26/0057H01L 21/565H01L 21/6836H01L 2225/06582H01L 23/544H01L 21/67092B23K 2201/40H01L 22/12H01L 21/304H01L 22/32H01L 21/78H01L 25/065
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Claims

Abstract

To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising a wiring board and a semiconductor chip mounted on the wiring board,
 wherein the semiconductor chip has a region at own outer periphery where a test pad is arranged.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the semiconductor device has a structure in which a plurality of the semiconductor chips are stacked.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein a wiring layer on a main surface of the semiconductor chip has a low-dielectric-constant film in a method of manufacturing the semiconductor device.

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