Pre-fetching in a memory system configured with synthesized logical blocks

Abstract

A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

What is claimed is: 
     
         1 . A memory system that is capable of being connected to a host, the system comprising:
 a memory that includes first and second parallel operation elements, the first parallel operation element including a non-volatile memory cell array having a plurality of first storage regions and a first buffer, and the second parallel operation element including a non-volatile memory cell array having a plurality of second storage regions and a second buffer; and   a memory controller configured to perform operations on the memory based on first group information and second group information, the first group information defining one or more first groups, each of the first groups including one of the first storage regions and one of the second storage regions and each of the second groups including at least two of the first groups, wherein   the memory controller, in response to a command from the host targeting one of the first storage regions, (i) acquires first data, which is data targeted by the command, from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer, and   the first storage region in which the first data is stored and the second storage region in which the second data is stored belong to different first groups and to the same second group.   
     
     
         2 . The memory system according to  claim 1 , wherein logical addresses of the first and second data are consecutive logical addresses. 
     
     
         3 . The memory system according to  claim 1 , wherein the first and second storage regions are each a physical block, and the first and second data are stored in different physical blocks. 
     
     
         4 . The memory system according to  claim 1 , wherein
 the first and second storage regions are each a physical block and the memory controller is configured to perform operations on the memory based also on defective block information which identifies physical blocks that are defective.   
     
     
         5 . The memory system according to  claim 1 , wherein the memory controller communicates with the first and second parallel operation elements over a shared first channel. 
     
     
         6 . The memory system according to  claim 5 , wherein the memory further includes third and fourth parallel operation elements, and the memory controller communicates with the third and fourth parallel operation elements over a shared second channel. 
     
     
         7 . The memory system according to  claim 1 , wherein the first parallel operation element further includes third storage regions and the second parallel operation element includes fourth storage regions, and each of the first groups further includes one of the third storage regions and one of the fourth storage regions. 
     
     
         8 . The memory system according to  claim 1 , further comprising:
 an error correction circuit configured to generate an error correction frame, wherein   the first and second storage regions are each a physical block divided into a plurality of pages, each page being a unit of data reading and writing, and   the error correction frame is generated from N pages of data, where N is equal to N 1 ×N 2 , where N 1  is the number of physical blocks in each of the first groups and N 2  is the number of first groups in each of the second groups.   
     
     
         9 . A method of prefetching data for subsequent read operation performed on a memory that includes first and second parallel operation elements, the first parallel operation element including a non-volatile memory cell array having a plurality of first storage regions and a first buffer, and the second parallel operation element including a non-volatile memory cell array having a plurality of second storage regions and a second buffer, said method comprising:
 in response to a read command from the host targeting one of the first storage regions, (i) acquiring first data, which is data targeted by the command, from the first buffer, and thereafter, (ii) causing the memory to readout second data to the first buffer, wherein   the first and second storage regions are grouped according to first group information and second group information, the first group information defining one or more first groups, each of the first groups including one of the first storage regions and one of the second storage regions and each of the second groups including at least two of the first groups, and   the first storage region in which the first data is stored and the second storage region in which the second data is stored belong to different first groups and to the same second group.   
     
     
         10 . The method according to  claim 9 , wherein logical addresses of the first and second data are consecutive logical addresses. 
     
     
         11 . The method according to  claim 9 , wherein the first and second storage regions are each a physical block, and the first and second data are stored in different physical blocks. 
     
     
         12 . The method according to  claim 11 , further comprising:
 tracking defective physical blocks; and   determining that the physical block storing the second data is not one of the defective physical blocks prior to reading the second data therefrom.   
     
     
         13 . The method according to  claim 9 , wherein the first and second parallel operation elements share a common communication channel. 
     
     
         14 . The method according to  claim 13 , wherein the memory further includes third and fourth parallel operation elements, and the third and fourth parallel operation elements share a common communication channel different from the one shared by the first and second parallel operation elements. 
     
     
         15 . The method according to  claim 9 , wherein the first parallel operation element further includes third storage regions and the second parallel operation element includes fourth storage regions, and each of the first groups further includes one of the third storage regions and one of the fourth storage regions. 
     
     
         16 . A computing device comprising:
 a host; and   a memory system including a host interface configured to communicate with the host, a memory that includes first and second parallel operation elements, the first parallel operation element including a non-volatile memory cell array having a plurality of first storage regions and a first buffer, and the second parallel operation element including a non-volatile memory cell array having a plurality of second storage regions and a second buffer, and a memory controller configured to perform operations on the memory based on first group information and second group information, the first group information defining one or more first groups, each of the first groups including one of the first storage regions and one of the second storage regions and each of the second groups including at least two of the first groups, wherein   the memory controller, in response to a command from the host targeting one of the first storage regions, (i) acquires first data, which is data targeted by the command, from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer, and   the first storage region in which the first data is stored and the second storage region in which the second data is stored belong to different first groups and to the same second group.   
     
     
         17 . The computing device according to claim.  16 , wherein logical addresses of the first and second data are consecutive logical addresses. 
     
     
         18 . The computing device according to claim.  16 , wherein the first storage regions are physical blocks, and the first and second data are stored in different physical blocks. 
     
     
         19 . The computing device according to claim.  16 , wherein the memory further includes third and fourth parallel operation elements, and the memory controller communicates with the first and second parallel operation elements over a shared first channel, and with the third and fourth parallel operation elements over a shared second channel. 
     
     
         20 . The computing device according to  claim 16 , wherein the first parallel operation element further includes third storage regions and the second parallel operation element includes fourth storage regions, and each of the first groups further includes one of the third storage regions and one of the fourth storage regions.