Semiconductor packages and methods of fabricating the same

Abstract

Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a lower package; and   a conductive layer in contact with at least one surface of the lower package,   wherein the lower package comprises:
 a lower substrate having a top surface and a ground pad; 
 a lower semiconductor chip mounted on the top surface of the lower substrate; and 
 a lower mold layer on the top surface of the lower substrate, the lower mold layer exposing a top surface of the lower semiconductor chip; 
   wherein the conductive layer is electrically connected to the ground pad.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the conductive layer is in direct contact with an outer side surface of the lower mold layer. 
     
     
         3 . The semiconductor package of  claim 2 , wherein the ground pad is exposed on a side surface of the lower substrate,
 wherein the conductive layer extends onto the side surface of the lower substrate.   
     
     
         4 . The semiconductor package of  claim 2 , further comprising an upper package on the lower package,
 wherein the conductive layer extends onto a side surface and a top surface of the upper package.   
     
     
         5 . The semiconductor package of  claim 2 , wherein the ground pad is exposed on a top surface of the lower substrate,
 wherein the conductive layer is in direct contact with the ground pad.   
     
     
         6 . The semiconductor package of  claim 4 , wherein the conductive layer comprises:
 a first metallic portion; and   a second metallic portion containing a different material from the first metallic portion.   
     
     
         7 . The semiconductor package of  claim 6 , each of the first and second metallic portions has a size that is greater than a size of a gap between the lower package and the upper package. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the conductive layer is in direct contact with the top surface of the lower semiconductor chip and a top surface of the lower mold layer. 
     
     
         9 . The semiconductor package of  claim 8 , wherein the conductive comprises a ground contact that passes through the lower mold layer and is electrically connected to the ground pad. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the ground pad is disposed on the top surface of the lower substrate. 
     
     
         11 . The semiconductor package of  claim 1 , wherein the lower mold layer has a top surface that is substantially coplanar with the top surface of the lower semiconductor chip; and
 wherein the top surfaces of the lower semiconductor chip and the lower mold layer have a difference in surface roughness from each other.   
     
     
         12 . The semiconductor package of  claim 1 , further an insulating layer provided between a gap between the lower and upper packages. 
     
     
         13 . A semiconductor package, comprising:
 a lower substrate having a top surface and a lower connection terminal on the top surface;   a lower semiconductor chip mounted on the top surface of the lower substrate;   a lower mold layer on the top surface of the lower substrate and exposing a top surface of the lower semiconductor chip, the lower mold layer having an opening exposing the lower connection terminal;   a first conductive layer in the opening of the lower mold layer and electrically connected to the lower connection terminal;   a second conductive layer on the top surface of the lower semiconductor chip and spaced apart from the first conductive layer;   an upper package on the first conductive layer and the second conductive layer.   
     
     
         14 . The semiconductor package of  claim 13 , wherein the first conductive layer and the second conductive layer are formed by using metal powder. 
     
     
         15 . The semiconductor package of  claim 13 , wherein the first conductive layer and the second conductive layer are formed by a cold spray process. 
     
     
         16 . The semiconductor package of  claim 13 , the first conductive layer and the second conductive layer are formed by a patterning a conductive layer,
 wherein the conductive layer covers the lower semiconductor chip and the lower mold layer and fills the opening.   
     
     
         17 . The semiconductor package of  claim 16 , the conductive layer is formed by spraying the metal powder. 
     
     
         18 . The semiconductor package of  claim 13 , further comprising an insulating layer provided between the lower semiconductor chip and the second conductive layer. 
     
     
         19 . The semiconductor package of  claim 13 , further comprising an upper connection terminal between the first conductive layer and the upper package, the upper connection terminal electrically connecting the upper package to the first conductive layer. 
     
     
         20 . The semiconductor package of  claim 13 , wherein upper package comprises:
 an upper substrate on the first conductive layer and the second conductive layer;   an upper semiconductor chip mounted on the upper substrate; and   an upper mold layer covering the upper semiconductor chip.