Method of making a semiconductor device using a dummy gate

Abstract

A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

1 . A semiconductor device, comprising:
 a first semiconductor layer having a first portion, a second portion, and a third portion;   a fin in the first portion of the first semiconductor layer;   a gate on the fin;   sidewall spacers adjacent to the gate;   a source region on the second portion of the first semiconductor layer and adjacent to a first side of the fin, the source region spaced apart from the gate by a first spacer of the sidewall spacers; and   a drain region on the third portion of the first semiconductor layer and adjacent to a second side of the fin, the drain region spaced apart from the gate by a second spacer of the sidewall spacers.   
     
     
         2 . The semiconductor device of  claim 1  wherein the sidewall spacers are on the fin. 
     
     
         3 . The semiconductor device of  claim 1  wherein the gate includes a dielectric layer and a polysilicon layer on the dielectric layer. 
     
     
         4 . The semiconductor device of  claim 1  wherein the fin extends between the second portion and the third portion of the first semiconductor layer. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 a second semiconductor layer; and   a dielectric layer on the second semiconductor layer, the first semiconductor layer being on the dielectric layer and spaced from the second semiconductor layer by the dielectric layer.   
     
     
         6 . The semiconductor device of  claim 1  wherein the first portion includes a surface that extends between the second portion and the third portion, and the fin protrudes from the surface of the first portion. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a fin mask layer between the fins and the gate. 
     
     
         8 . A semiconductor device, comprising:
 a first semiconductor layer having a first portion extending in a first direction and a fin extending in a second direction from the first portion, the second direction transverse to the first direction;   a source region and a drain region on the first portion of the first semiconductor layer;   sidewall spacers extending in the second direction from the fin of the first semiconductor layer;   a gate on the fin and between the sidewall spacers, the gate being spaced from the source region and the drain region by the sidewall spacers.   
     
     
         9 . The semiconductor device of  claim 8  wherein the gate includes a dielectric layer and a polysilicon layer on the dielectric layer. 
     
     
         10 . The semiconductor device of  claim 8  wherein the gate has a width in the first direction corresponding to a distance between inwardly facing side surfaces of the sidewall spacers. 
     
     
         11 . The semiconductor device of  claim 8 , further comprising:
 a second semiconductor layer; and   a dielectric layer on the second semiconductor layer, wherein the first semiconductor layer is on the dielectric layer and is spaced from the second semiconductor layer by the dielectric layer.   
     
     
         12 . The semiconductor device of  claim 8 , further comprising a fin mask layer on an upper surface of the fin, the fin mask layer spacing the upper surface from the gate. 
     
     
         13 . A device, comprising:
 a substrate;   a first dielectric layer on the substrate;   a semiconductor layer on the first dielectric layer, the semiconductor layer including a fin having a first surface that is spaced from a second surface of the semiconductor layer;   a gate on the first surface of the fin of the semiconductor layer;   sidewall spacers on the first surface of the fin adjacent to the gate;   a source region on the second surface of the semiconductor layer; and   a drain region on the second surface of the semiconductor layer, the fin and the gate being between the source and drain.   
     
     
         14 . The device of  claim 13 , further comprising a fin mask layer on the fin between the first surface and the gate. 
     
     
         15 . The device of  claim 13  wherein the source region and the drain region are spaced from the gate by the sidewall spacers. 
     
     
         16 . The device of  claim 13 , further comprising a second dielectric layer on the source region and the drain region, the second dielectric layer begin adjacent to the sidewall spacers. 
     
     
         17 . The device of  claim 16  wherein a surface of the second dielectric layer is coplanar with an upper surface of the gate.