Methods for mitigating power loss events during operation of memory devices and memory devices employing the same

Abstract

Memory devices and methods for operating the same are described. The memory devices may include non-volatile memory having a plurality of memory cells, and a controller. The controller may be configured to begin a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information, terminate the first programming operation in response to detecting a power loss event, and program, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information.

I/We claim: 
     
         1 . A memory device, comprising:
 a non-volatile memory comprising a plurality of memory cells; and   a controller configured to:
 begin a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information, 
 terminate the first programming operation in response to detecting a power loss event, and 
 program, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information. 
   
     
     
         2 . The memory device of  claim 1 , wherein:
 the second programming operation requires less energy to program the second and third ones of the plurality of memory cells in less time than the first programming operation would have taken to complete.   
     
     
         3 . The memory device of  claim 1 , wherein:
 the second programming operation is configured to program the second and third ones of the plurality of memory cells in less time than the first programming operation would have taken to complete.   
     
     
         4 . The memory device of  claim 1 , wherein:
 the first programming operation is configured to program the first one of the plurality of memory cells with a first plurality of programming pulses, and   the second programming operation is configured to program each of the second and third ones of the plurality of memory cells with fewer programming pulses than the first plurality of programming pulses.   
     
     
         5 . The memory device of  claim 1 , wherein:
 the second programming operation is configured to program each of the second and third ones of the plurality of memory cells with one bit of information of the more than one bit of information.   
     
     
         6 . The memory device of  claim 1 , wherein:
 the first one of the plurality of memory cells is configured as a triple level cell which has already been programmed with lower page data and upper page data prior to the first programming operation, and   the first programming operation is configured to program extra page data to the first one of the plurality of memory cells.   
     
     
         7 . The memory device of  claim 6 , wherein:
 the second programming operation is configured to program the lower page data to the second one of the plurality of memory cells and to program the upper page data to the third one of the plurality of memory cells.   
     
     
         8 . The memory device of  claim 7 , wherein:
 the second programming operation is further configured to program the extra page data to a fourth one of the plurality of memory cells.   
     
     
         9 . The memory device of  claim 7 , wherein:
 each of the second and third ones of the plurality of memory cells is configured as a single level cell.   
     
     
         10 . The memory device of  claim 1 , further comprising:
 one or more energy storage components configured to store an amount of energy sufficient to complete the second programming operation after the power loss event.   
     
     
         11 . The memory device of  claim 10 , wherein:
 the amount of energy is insufficient to complete the first programming operation after the power loss event.   
     
     
         12 . The memory device of  claim 10 , wherein:
 the one or more energy storage components comprise one or more capacitors.   
     
     
         13 . The memory device of  claim 1 , wherein the first one of the plurality of memory cells is located in a first memory block, and wherein the second and third ones of the plurality of memory cells are located in a second memory block. 
     
     
         14 . A memory device, comprising:
 one or more energy storage components configured to store an amount of energy;   a non-volatile memory comprising a plurality of memory cells; and   a controller configured to:
 begin a first programming operation configured to program more than one bit of information to a first one of the plurality of memory cells, wherein the first programming operation requires more than the stored amount of energy to complete, 
 terminate the first programming operation in response to detecting a power loss event, and 
 program, with a second programming operation utilizing the stored amount of energy, second and third ones of the plurality of memory cells with the more than one bit of information. 
   
     
     
         15 . The memory device of  claim 14 , wherein:
 the first one of the plurality of memory cells is configured as a triple level cell which has already been programmed with lower page data and upper page data prior to the first programming operation, and   the first programming operation is configured to program extra page data to the first one of the plurality of memory cells.   
     
     
         16 . The memory device of  claim 15 , wherein:
 the second programming operation is configured to program the lower page data to the second one of the plurality of memory cells and to program the upper page data to the third one of the plurality of memory cells.   
     
     
         17 . The memory device of  claim 16 , wherein:
 the second programming operation is further configured to program the extra page data to a fourth one of the plurality of memory cells.   
     
     
         18 . The memory device of  claim 17 , wherein:
 each of the second, third and fourth ones of the plurality of memory cells is configured as a single level cell.   
     
     
         19 . The memory device of  claim 14 , wherein:
 the more than one bit of information comprises two bits of information, and wherein the second and third ones of the plurality of memory cells are each programmed with one bit of information of the two bits of information.   
     
     
         20 . The memory device of  claim 14 , wherein:
 the more than one bit of information comprises three bits of information, and wherein the second and third ones of the plurality of memory cells are each programmed with one bit of information of the three bits of information, and a third bit of information of the three bits of information is not programmed to any of the plurality of memory cells.   
     
     
         21 . The memory device of  claim 14 , wherein:
 the more than one bit of information comprises three bits of information, and wherein the second and third ones of the plurality of memory cells are each programmed with one bit of information of the three bits of information, and a third bit of information of the three bits of information is programmed to a fourth one of the plurality of memory cells.   
     
     
         22 . The memory device of  claim 14 , wherein:
 the more than one bit of information comprises more than three bits of information, and wherein the second one of the plurality of memory cells is programmed with more than one bit of information of the more than three bits of information.   
     
     
         23 . A method of operating a memory device having a plurality of memory cells, the method comprising:
 initiating a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information,   terminating the first programming operation in response to detecting a power loss event, and   programming, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information.   
     
     
         24 . The method of  claim 23 , further comprising:
 programming, with the second programming operation, a fourth one of the plurality of memory cells with at least one bit of information of the more than one bit of information.   
     
     
         25 . The method of  claim 23 , further comprising:
 determining, upon powering the memory device, that the second programming operation was performed, and   completing the first programming operation with the more than one bit of information from the second and third ones of the plurality of memory cells.   
     
     
         26 . A method of operating a memory device having a plurality of memory cells, the method comprising:
 determining, upon powering the memory device, that a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information was terminated in response to detecting a power loss event, and   completing the first programming operation with the more than one bit of information from second and third ones of the plurality of memory cells.