Metal Oxide Thin Film Semiconductor Device Monolithically Integrated With Dissimilar Device on the Same Wafer

Abstract

A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof.

1 . A monolithically integrated circuit comprising:
 a semiconducting wafer;   a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer; and   a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer.   
     
     
         2 . The monolithically integrated circuit of  claim 1  wherein the dissimilar semiconductor device is a compound semiconductor transistor. 
     
     
         3 . The monolithically integrated circuit of  claim 1  further comprising an electrically conducting interconnect layer connecting the metal oxide thin film semiconductor device to the dissimilar semiconductor device. 
     
     
         4 . The monolithically integrated circuit of  claim 1  wherein the semiconducting wafer comprises an alloy of two or more of indium, gallium, aluminum, phosphorus, nitrogen, and arsenic. 
     
     
         5 . The monolithically integrated circuit of  claim 4  wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor gate embedded in the semiconducting wafer. 
     
     
         6 . The monolithically integrated circuit of  claim 1  wherein the dissimilar semiconductor device is electrically isolated from the first region of the semiconducting wafer. 
     
     
         7 . The monolithically integrated circuit of  claim 1  wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor device gate and a metal oxide thin film semiconductor device dielectric layer and the dissimilar semiconductor device includes a dissimilar semiconductor device gate and a dissimilar semiconductor device passivation layer, at least one of the metal oxide thin film semiconductor device gate and metal oxide thin film semiconductor device dielectric layer being formed from a same material and concurrently with the dissimilar semiconductor device gate and the dissimilar semiconductor device passivation layer, respectively. 
     
     
         8 . A monolithically integrated circuit comprising:
 a semiconducting wafer comprising an alloy of two or more of indium, gallium, aluminum, phosphorus, nitrogen, and arsenic;   a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer;   a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer, the dissimilar semiconductor device being electrically isolated from the first region of the semiconducting wafer; and   an electrically conducting interconnect layer connecting the metal oxide thin film semiconductor device to the dissimilar semiconductor device.   
     
     
         9 . The monolithically integrated circuit of  claim 8  wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor gate embedded in the semiconducting wafer. 
     
     
         10 . The monolithically integrated circuit of  claim 8  wherein the dissimilar semiconductor device is a compound semiconductor transistor. 
     
     
         11 . The monolithically integrated circuit of  claim 8  wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor device gate and a metal oxide thin film semiconductor device dielectric layer and the dissimilar semiconductor device includes a dissimilar semiconductor device gate and a dissimilar semiconductor device passivation layer, at least one of the metal oxide thin film semiconductor device gate and metal oxide thin film semiconductor device dielectric layer being formed from a same material and concurrently with the dissimilar semiconductor device gate and the dissimilar semiconductor device passivation layer, respectively. 
     
     
         12 . A method of forming a monolithically integrated circuit on a semiconducting wafer, the method comprising:
 forming a metal oxide thin film semiconductor device adjacent a first region of the semiconducting wafer; and   forming a dissimilar semiconductor device on a second region of the semiconducting wafer.   
     
     
         13 . The method of  claim 12  wherein the dissimilar semiconductor device includes a thermal budget and the metal oxide thin film semiconductor device is formed in processing conditions that do not exceed the thermal budget of the dissimilar semiconductor device. 
     
     
         14 . The method of  claim 12  wherein the metal oxide thin film semiconductor device and dissimilar semiconductor device are formed concurrently in a front end of line process. 
     
     
         15 . The method of  claim 14  further comprising depositing one or more insulating layers adjacent the dissimilar semiconductor device gate for passivation of the dissimilar semiconductor device prior to forming at least some layers of the metal oxide thin film semiconductor device. 
     
     
         16 . The method of  claim 15  wherein at least one of the one or more insulating layers is deposited adjacent the first region of the semiconducting wafer for forming a dielectric film for the metal oxide thin film semiconductor device concurrently with being deposited adjacent the dissimilar semiconductor device gate. 
     
     
         17 . The method of  claim 14  wherein the metal oxide thin film semiconductor device includes a metal oxide thin film semiconductor device gate and the dissimilar semiconductor device includes a dissimilar semiconductor device gate, the metal oxide thin film semiconductor device gate being formed from a same material and concurrently with the dissimilar semiconductor device gate. 
     
     
         18 . The method of  claim 14  further comprising:
 forming a metal oxide thin film semiconductor device gate adjacent the first region of the semiconducting wafer and a dissimilar semiconductor device gate adjacent the second region of the semiconducting wafer; 
 depositing a metal oxide thin film semiconductor device insulating layer adjacent the metal oxide thin film semiconductor device gate and over the dissimilar semiconductor device gate; 
 depositing a metal oxide thin film semiconductor device semiconducting layer adjacent the metal oxide thin film semiconductor device insulating layer; and 
 removing at least a portion of the metal oxide thin film semiconductor device insulating layer and the metal oxide thin film semiconductor device semiconducting layer from the second region of the semiconducting wafer. 
 
     
     
         19 . The method of  claim 18  further comprising depositing a protective layer over the dissimilar semiconductor device gate prior to depositing the metal oxide thin film semiconductor device semiconducting layer. 
     
     
         20 . The method of  claim 12  further comprising forming electrically conducting interconnects between the metal oxide thin film semiconductor device and the dissimilar semiconductor device.