Vertical Transistor Device with a Variable Gate Dielectric Thickness

Abstract

A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate trench, a source region adjacent the gate trench and above the body region, and a dielectric material covering a bottom and a sidewall of the gate trench. A thickness of the dielectric material is greater at the bottom of the gate trench than along the sidewall of the gate trench. Further vertical transistor device embodiments and corresponding methods of manufacture are also described.

What is claimed is: 
     
         1 . A vertical transistor device, comprising:
 a silicon-carbide substrate;   a gate trench formed in the silicon-carbide substrate;   a body region adjacent the gate trench;   a source region adjacent the gate trench and above the body region; and   a dielectric material covering a bottom and a sidewall of the gate trench, a thickness of the dielectric material being greater at the bottom of the gate trench than along the sidewall of the gate trench.   
     
     
         2 . The vertical transistor device of  claim 1 , wherein the gate dielectric comprises:
 a first dielectric layer formed only along the bottom of the gate trench and not the sidewall; and   a second dielectric layer formed along the bottom and the sidewall of the gate trench.   
     
     
         3 . The vertical transistor device of  claim 1 , wherein the sidewall of the gate trench is aligned with a crystallographic plane of the silicon-carbide substrate. 
     
     
         4 . The vertical transistor device of  claim 3 , wherein the sidewall of the gate trench is aligned with a 11−20 crystallographic plane of the silicon-carbide substrate. 
     
     
         5 . The vertical transistor device of  claim 1 , wherein the sidewall of the gate trench is angled between 85 to 87 degrees relative to a main surface of the silicon-carbide substrate. 
     
     
         6 . The vertical transistor device of  claim 1 , wherein the sidewall of the gate trench extends to a first lower rounded corner of the gate trench, and wherein an additional sidewall of the gate trench extends to a second lower rounded corner of the gate trench opposite the first lower rounded corner. 
     
     
         7 . The vertical transistor device of  claim 6 , wherein the gate dielectric has a uniform thickness at the first and the second lower rounded corners. 
     
     
         8 . The vertical transistor device of  claim 1 , further comprising a doped region of a same conductivity type as the body region extending from a main surface of the silicon-carbide substrate, along the sidewall of the gate trench and below the bottom of the gate trench. 
     
     
         9 . The vertical transistor device of  claim 8 , further comprising an additional doped region of the same conductivity type as the body region and disposed in a drift region of the silicon-carbide substrate disposed below the body region, wherein the doped region extends into the additional doped region. 
     
     
         10 . A vertical transistor device, comprising:
 a silicon-carbide substrate;   a plurality of gate trenches formed in the silicon-carbide substrate;   a SiC mesa disposed between adjacent ones of the gate trenches, the SiC mesa including a body region and a source region above the body region; and   a dielectric material covering a bottom and a sidewall of the gate trenches, a thickness of the dielectric material being greater at the bottom of the gate trenches than along the sidewall of the gate trench.   
     
     
         11 . The vertical transistor device of  claim 10 , wherein the gate dielectric comprises:
 a first dielectric layer formed only along the bottom of the gate trenches and not the sidewall; and   a second dielectric layer formed along the bottom and the sidewall of the gate trenches.   
     
     
         12 . The vertical transistor device of  claim 10 , wherein the sidewall of each of the gate trenches is aligned with a crystallographic plane of the silicon-carbide substrate. 
     
     
         13 . The vertical transistor device of  claim 12 , wherein the sidewall of each of the gate trenches is aligned with a 11−20 crystallographic plane of the silicon-carbide substrate. 
     
     
         14 . The vertical transistor device of  claim 10 , wherein the sidewall of each of the gate trenches is angled between 85 to 87 degrees relative to a main surface of the silicon-carbide substrate. 
     
     
         15 . The vertical transistor device of  claim 10 , wherein the sidewall of each of the gate trenches extends to a first lower rounded corner, and wherein an additional sidewall of each of the gate trenches extends to a second lower rounded corner opposite the first lower rounded corner. 
     
     
         16 . The vertical transistor device of  claim 15 , wherein the gate dielectric has a uniform thickness at the first and the second lower rounded corners of each of the gate trenches. 
     
     
         17 . The vertical transistor device of  claim 10 , further comprising a plurality of doped regions of a same conductivity type as the body region extending from a main surface of the silicon-carbide substrate, along the sidewall of the gate trenches and below the bottom of the gate trenches. 
     
     
         18 . The vertical transistor device of  claim 17 , further comprising a plurality of additional doped regions of the same conductivity type as the body region, disposed in a drift region of the silicon-carbide substrate below the body region, and laterally spaced apart from one another, wherein each one of the doped regions vertically extends into one of the additional doped regions. 
     
     
         19 . A method of manufacturing a vertical transistor device, the method comprising:
 forming a body region and a source region above the body region in a silicon-carbide substrate;   forming a gate trench in the silicon-carbide substrate, the gate trench being adjacent the body region and the source region; and   covering a bottom and a sidewall of the gate trench with a dielectric material, a thickness of the dielectric material being greater at the bottom of the gate trench than along the sidewall of the gate trench.   
     
     
         20 . The method of  claim 19 , wherein covering the bottom and the sidewall of the gate trench with a dielectric material comprises:
 forming a first dielectric layer only along the bottom of the gate trench and not the sidewall; and   forming a second dielectric layer along the bottom and the sidewall of the gate trench.