Method and system for receiver configuration based on a priori knowledge of noise

Abstract

Methods and systems are provided for using priori knowledge of noise in controlling signal receivers. In a signal receiver, one or more adjustments, relating to generating output signals via the signal receiver, may be determined, with the adjustments directed to one or more particular components of the output signals. When applying the adjustments is determined to cause undesired effects on one or more other components of the output signals, with these other components being intended to remain unchanged when the adjustments are applied, operations of the signal receiver may be controlled based on the undesired effects, with the controlling including mitigating at least some of the effects on the one or more other components of the signals when the one or more adjustments are applied. The adjustments may include frequency re-assignment. The undesired effects may include one or more of amplitude glitches, phase glitches, bit or packet errors, etc.

1 - 20 . (canceled) 
     
     
         21 . A method for processing signals in a signal receiver, comprising:
 determining one or more adjustments relating to generating output signals via said signal receiver, wherein said one or more adjustments are directed to one or more components of said output signals;   determining when applying said one or more adjustments causes undesired effects on one or more other components of said output signals, wherein said one or more other components are intended to remain unchanged when said one or more adjustments are applied; and   controlling operations of said signal receiver based on said undesired effects, said controlling comprising mitigating at least some of said effects on said one or more other components of said signals when said one or more adjustments are applied.   
     
     
         22 . The method of  claim 21 , wherein said one or more adjustments comprise frequency re-assignment. 
     
     
         23 . The method of  claim 21 , wherein said undesired effects comprise one or more of amplitude glitches, phase glitches, and bit or packet errors. 
     
     
         24 . The method of  claim 21 , wherein said controlling of operations of said signal receiver comprises adjusting one or more parameters used during signal processing in said signal receiver. 
     
     
         25 . The method of  claim 24 , wherein said adjusting of said one or more parameters comprises adjusting amplification gain used during said signal processing. 
     
     
         26 . The method of  claim 24 , wherein said adjusting of said one or more parameters comprises adjusting tracking loop bandwidth used during said signal processing. 
     
     
         27 . The method of  claim 24 , wherein said adjusting of said one or more parameters comprises adjusting set points applied to analog-to-digital conversion performed during said signal processing. 
     
     
         28 . The method of  claim 21 , comprising:
 determining when said undesired effects comprise bit or packet errors caused by applying said one or more adjustments; and   modifying or changing error handling related functions based on said determination.   
     
     
         29 . The method of  claim 28 , comprising modifying or changing said error handling related functions to ignore said bit or packet errors caused by applying said one or more adjustments. 
     
     
         30 . A system, comprising:
 one or more processing circuits that:
 process input signals to said system; and 
 generated corresponding output signals based on said processing; and 
   one or more control circuits that:
 determine one or more adjustments relating to generating said output signals, wherein said one or more adjustments are directed to one or more components of said output signals; 
 determine when applying said one or more adjustments causes undesired effects on one or more other components of output signals, wherein said one or more other components are intended to remain unchanged when said one or more adjustments are applied; and 
 control operations of said one or more processing circuits based on said undesired effects, wherein said controlling comprises mitigating at least some of said undesired effects when said one or more adjustments are applied. 
   
     
     
         31 . They system of  claim 30 , wherein said one or more processing circuits comprise at least one of a tuner circuit, an amplifier circuit, an analog-to-digital convertor (ADC) circuit, and a demodulator circuit. 
     
     
         32 . The system of  claim 30 , wherein said one or more control circuits, when controlling said operations of said one or more processing circuit, set or modify one or more parameters applied to or associated with said one or more processing circuits. 
     
     
         33 . The system of  claim 30 , wherein said one or more processing circuits comprise an amplifier circuit; and
 said one or more control circuits adjust amplification gain applied via said amplifier circuit, when controlling said operations of said one or more processing circuits.   
     
     
         34 . The system of  claim 30 , wherein said one or more processing circuits comprise an carrier tracking loop (CTL) circuit; and
 said one or more control circuits adjust tracking bandwidth utilized by said CTL circuit, when controlling said operations of said one or more processing circuits.   
     
     
         35 . The system of  claim 30 , wherein said one or more processing circuits comprise an analog-to-digital convertor (ADC) circuit; and
 said one or more control circuits adjust set points applied to said ADC circuit, when controlling said operations of said one or more processing circuits.   
     
     
         36 . The system of  claim 30 , wherein said one or more control circuits:
 determine when said undesired effects comprise bit or packet errors; and   modify or change error handling related functions based on said determination.   
     
     
         37 . The system of  claim 36 , wherein said one or more control circuits modify or change said error handling related functions to ignore said bit or packet errors when applying said one or more adjustments. 
     
     
         38 . The system of  claim 30 , comprising a signal reception assembly that captures satellite signals; and wherein said one or more processing circuits process said satellite signals. 
     
     
         39 . The system of  claim 30 , wherein said one or more processing circuits handled channel-stacked signals.