Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device having a trench-gate field effect transistor formed in a semiconductor substrate, comprising:
 a trench made in the semiconductor substrate;   a gate electrode for the trench-gate field effect transistor, formed in the trench through a gate insulating film;   a diode device formed through a first insulating film over the semiconductor substrate; and   an interlayer insulating film formed over a main surface of the semiconductor substrate,   wherein an upper surface of the gate electrode is in a lower position than an upper surface of the semiconductor substrate in an area adjacent to the trench,   wherein a sidewall insulating film is formed over the gate electrode and over a sidewall of the trench,   wherein the gate electrode and the sidewall insulating film are covered by the interlayer insulating film, and   wherein the sidewall insulating film is formed from an insulating film in the same layer as the first insulating film.   
     
     
         22 . The semiconductor device according to  claim 21 , further comprising:
 a semiconductor region for a source of first conductivity type which is formed in an area adjacent to the trench in the semiconductor substrate;   a semiconductor region for channel formation of second conductivity type opposite to the first conductivity type which is located under the semiconductor region for the source; and   a semiconductor region for a drain of the first conductivity type which is located under the semiconductor region for channel formation.   
     
     
         23 . The semiconductor device according to  claim 22 ,
 wherein the sidewall insulating film has a shape of sidewall spacer.   
     
     
         24 . The semiconductor device according to  claim 22 ,
 wherein the upper surface of the gate electrode is in a lower position than an upper surface of the semiconductor region for the source and in a higher position than a boundary between the semiconductor region for the source and the semiconductor region for channel formation.   
     
     
         25 . The semiconductor device according to  claim 21 ,
 wherein the gate insulating film extends between the sidewall insulating film and the sidewall of the trench.   
     
     
         26 . The semiconductor device according to  claim 21 ,
 wherein the diode device is formed from a silicon film formed over the first insulating film.   
     
     
         27 . The semiconductor device according to  claim 21 ,
 wherein thickness of the gate insulating film in an upper portion of the trench is smaller than thickness of the gate insulating film in a lower portion of the trench.   
     
     
         28 . The semiconductor device according to  claim 21 , further comprising a first electrode formed in a lower portion of the trench,
 wherein the gate electrode is formed in an upper portion of the trench, and   wherein the gate insulating film is formed between the sidewall and a bottom of the trench and the first electrode, between the sidewall of the trench and the gate electrode, and between the first electrode and the gate electrode.   
     
     
         29 . The semiconductor device according to  claim 22 , further comprising:
 a contact hole penetrating the interlayer insulating film;   a conductor filling the contact hole; and   a wiring formed over the interlayer insulating film,   wherein the wiring includes a source wiring, and   wherein the source wiring is electrically coupled to the semiconductor region for the source and the semiconductor region for channel formation through the conductor.